公开(公告)号：US3906286A

公开(公告)日：1975-09-16

申请号：US44181274

申请日：1974-02-12

Applicant: NIPPON ELECTRIC CO

Inventor： AKAHANE FUMITAKE ,  IWAKAWA TSUNEKIYO ,  IMAI HIDEYO ,  OKAZAKI HIROSHI ,  WADA TOSHIO

IPC: H01J31/15 ,  H01J63/02

CPC classification number: H01J31/15

Abstract: An indicator tube having an anode structure and a hot cathode placed in front of the structure. The structure comprises a base plate and a plurality of phosphor anode segments which are capable of displaying at least one numeric, alphabetic, or similar figure. The tube dispenses with the conventionally required mask by embedding the anode segments within the base plate.

Abstract translation: 具有放置在结构前面的阳极结构和热阴极的指示管。 该结构包括基板和多个能够显示至少一个数字，字母或类似图形的荧光体阳极段。 通过将阳极段嵌入基板内，管分配常规所需的掩模。

公开(公告)号：US3535601A

公开(公告)日：1970-10-20

申请号：US3535601D

申请日：1968-07-30

Applicant: NIPPON ELECTRIC CO

Inventor： MATSUKURA YASUO ,  OHTA KUNIICHI ,  WADA TOSHIO

IPC: H01L47/00 ,  H03B9/12 ,  H01L11/00

CPC classification number: H03B9/12 ,  H01L47/00

公开(公告)号：US3532921A

公开(公告)日：1970-10-06

申请号：US3532921D

申请日：1968-08-16

Applicant: NIPPON ELECTRIC CO

Inventor： AKABANE FUITAKE ,  IWAKAWA TSUNEKIYO ,  IAMI HIDEYO ,  OKAZAKI HIROSHI ,  WADA TOSHIO

IPC: H01J29/18 ,  H01J31/15 ,  H01J7/42 ,  H01K1/60

CPC classification number: H01J29/18 ,  H01J31/15

公开(公告)号：US3663871A

公开(公告)日：1972-05-16

申请号：US3663871D

申请日：1970-02-16

Applicant: NIPPON ELECTRIC CO

Inventor： NAKANUMA SHO ,  TSUJIDE TOHRU ,  WADA TOSHIO

IPC: H01L21/283 ,  G11C16/04 ,  G11C17/00 ,  H01L21/28 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L29/00 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L11/14

CPC classification number: H01L29/792 ,  G11C16/04 ,  G11C16/0466 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/28167 ,  H01L21/31616 ,  H01L21/3162 ,  H01L29/00

Abstract: A metal-insulator-semiconductor (MIS) semiconductor read-only memory element employs, as the gate insulator film, an alumina film formed through a novel hydrolytic deposition process.

Abstract translation: 金属绝缘体半导体（MIS）半导体只读存储元件采用通过新的水解沉积工艺形成的氧化铝膜作为栅极绝缘膜。

公开(公告)号：US3651490A

公开(公告)日：1972-03-21

申请号：US3651490D

申请日：1970-06-08

Applicant: NIPPON ELECTRIC CO

Inventor： ONODA KATSUHIRO ,  IGARASHI RYO ,  WADA TOSHIO ,  NAKANUMA SHO ,  TSUJIDE TORU

IPC: G11C16/04 ,  G11C11/40

CPC classification number: G11C16/0466

Abstract: A three-dimensional memory includes MIS-type transistors as the memory elements formed on a plurality of integrated matrix boards. The transistor includes an insulating film capable of storing an electric charge in response to the application of a voltage across the gate and substrate exceeding a critical value. The row and column drive lines are respectively connected to row and column select circuitry, and a third select circuit applies a select voltage to one of the matrix boards.

Abstract translation: 三维存储器包括形成在多个集成矩阵板上的存储元件的MIS型晶体管。 晶体管包括能够响应于栅极和衬底上施加超过临界值的电压而存储电荷的绝缘膜。 行和列驱动线分别连接到行和列选择电路，并且第三选择电路将选择电压施加到矩阵板之一。

公开(公告)号：US3619740A

公开(公告)日：1971-11-09

申请号：US3619740D

申请日：1969-10-28

Applicant: NIPPON ELECTRIC CO

Inventor： NAKANUMA SHO ,  HANETA YUICHI ,  WADA TOSHIO

IPC: H01L21/74 ,  H01L21/82 ,  H01L23/29 ,  H01L27/085 ,  H01L19/00

CPC classification number: H01L27/085 ,  H01L21/74 ,  H01L21/82 ,  H01L23/291 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit is disclosed in which the drain and source regions of an integrated gate-type field-effect transistor and the gate region of a junction-type field-effect transistor are formed in common within a semiconductor layer of one conductivity type formed on a substrate of the opposite conductivity type.

公开(公告)号：US3665423A

公开(公告)日：1972-05-23

申请号：US3665423D

申请日：1970-03-13

Applicant: NIPPON ELECTRIC CO

Inventor： NAKANUMA SHO ,  TSUJIDE TOHRU ,  WADA TOSHIO ,  IGARASHI RYO ,  ONODA KATSUHIRO

IPC: H01L21/283 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8247 ,  H01L29/51 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC classification number: G11C16/0466 ,  H01L29/511 ,  H01L29/792

Abstract: A memory matrix device is disclosed in which an MIS semiconductor element is employed as the memory element. The semiconductor element has an insulating film disposed between the semiconductor substrate and conductor electrode. That film contains capture centers which capture electrons upon the application of a voltage exceeding a critical value across the electrode and substrate.

公开(公告)号：US3651348A

公开(公告)日：1972-03-21

申请号：US3651348D

申请日：1969-10-03

Applicant: NIPPON ELECTRIC CO

Inventor： MATSUKURA YASUO ,  WADA TOSHIO ,  OHTA KUNIICHL

IPC: H03K19/02 ,  H03K19/08

CPC classification number: H03K19/02

Abstract: A logic device comprises a Gunn effect element having a capacitive element connected across its electrodes. The Gunn effect element is normally biased below the threshold value, and an input pulse is applied to raise the internal field of the Gunn effect element above the threshold value. The resultant charging of the capacitive element causes the Gunn effect element to be maintained in a state of oscillation.

Abstract translation: 逻辑器件包括具有连接在其电极上的电容元件的Gunn效应元件。 Gunn效应元件通常偏置在阈值以下，并且施加输入脉冲以将Gunn效应元件的内部场提高到阈值以上。 电容元件的最终充电使得Gunn效应元件保持在振荡状态。

公开(公告)号：US3646527A

公开(公告)日：1972-02-29

申请号：US3646527D

申请日：1970-03-31

Applicant: NIPPON ELECTRIC CO

Inventor： WADA TOSHIO ,  ONODA KATSUHIRO ,  IGARASHI RYO ,  NAKANUMA SHO ,  TSUJIDE TOHRU

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/00 ,  H01L29/51 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40 ,  H01L13/00

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L29/00 ,  H01L29/51

Abstract: Data is written into a memory storage device by applying a negative voltage to the gate electrode of an MIS-type transistor, and a positive voltage to at least one of the drain and source of that transistor. The voltage difference between the gate and the source or drain exceeds a critical voltage so that electrons are injected and trapped in the gate film. Also disclosed is a memory matrix in which a plurality of MIS transistors are arranged in a matrix array and have their gate and source-drain electrodes connected to row-and-column drive lines.

公开(公告)号：US3582725A

公开(公告)日：1971-06-01

申请号：US3582725D

申请日：1969-08-21

Applicant: NIPPON ELECTRIC CO

Inventor： MATUKURA YASUO ,  NAKANUMA SHO ,  WADA TOSHIO

IPC: H01L21/74 ,  H01L21/761 ,  H01L21/82 ,  H01L5/00 ,  H01L7/02

CPC classification number: H01L21/82 ,  H01L21/74 ,  H01L21/761 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/151 ,  Y10S257/918

Abstract: According to the present invention, there is provided a semiconductor integrated circuit device comprising a semiconductor substrate of a first conductivity type; two opposite conductivity type buried layer regions, both with high impurity concentration but with different outward diffusion speeds, formed within said substrate, the region with the faster speed surrounding the other; and epitaxial layer of the first conductivity type epitaxially grown over said substrate allowing the impurities of said buried layer regions to outwardly diffuse thereinto; a diffusion region of the second conductivity type formed by diffusing second conductivity type impurities from the surface of said epitaxial layer in alignment with the buried layer of the higher outward diffusion speed; and isolated region of the higher outward diffusion speed; an isolated region of the first conductivity type thereby simultaneously formed on the surface of the buried layer of lower outward diffusion speed and surrounded by the diffusion region; an isolation region comprised of part of the epitaxial layer also simultaneously formed on the substrate surrounding the diffusion regions, and finally, metal wiring film attached to each of the regions. The two regions of the buried layer may be formed by using different impurities or by using different concentrations of the same impurity.