公开(公告)号：US07679737B2

公开(公告)日：2010-03-16

申请号：US11971384

申请日：2008-01-09

申请人： Naohiro Takahashi ,  Kiyoshi Irino

发明人： Naohiro Takahashi ,  Kiyoshi Irino

IPC分类号： G01N21/00

CPC分类号： G01N21/9501 ,  G01N21/4738

摘要： A method of inspecting defects on an object includes irradiating predetermined particles with a laser beam to measure first scattered light intensities, irradiating plural types of defects with the laser beam to measure second scattered light intensities, determining types of some defects selected out of the plural types of defects using the first scattered light intensities, setting a discrimination line indicating a boundary value of the second scattered light intensities based on the determination, and discriminating, using the discrimination line, defects on the object.

摘要翻译： 检查物体上的缺陷的方法包括用激光束照射预定粒子以测量第一散射光强度，用激光束照射多种类型的缺陷以测量第二散射光强度，确定多种类型中选择的某些缺陷的类型 使用第一散射光强度的缺陷，基于该确定来设置表示第二散射光强度的边界值的判别线，以及使用判别线识别物体上的缺陷。

公开(公告)号：US07340352B2

公开(公告)日：2008-03-04

申请号：US11588319

申请日：2006-10-27

申请人： Naohiro Takahashi ,  Kiyoshi Irino

发明人： Naohiro Takahashi ,  Kiyoshi Irino

IPC分类号： G01B5/28 ,  G06F19/00

CPC分类号： G01N21/9501 ,  G01N21/9503

摘要： An inspecting method is capable of efficiently inspecting a wafer. According to the inspecting method, the chip area of a wafer is inspected for defects, and based on the results, a defect density D0p of each of peripheral-zone chips in the chip area which are located closely to the peripheral area of the wafer is calculated. A peripheral-zone chip with a high defect density D0p is selected, and an area in the peripheral area which is outward of the selected peripheral-zone chip is inspected for defects. Since only the area in the peripheral area which is located outward of the peripheral-zone chip selected based on the defect density D0p is inspected for defects, the wafer is inspected efficiently.

摘要翻译： 检查方法能够有效地检查晶片。 根据检查方法，检查晶片的芯片面积的缺陷，并且基于该结果，芯片区域中的每个周边区域芯片的缺陷密度D 0p 位于紧密的位置 计算晶圆的外围区域。 选择具有高缺陷密度D <0P 的周边区域芯片，并且检查在所选周边区域芯片外部的周边区域中的缺陷。 由于仅考虑了基于缺陷密度D 0p <0>的所选外围区域芯片周边区域的区域，故有效地检查晶片。

公开(公告)号：US20070255513A1

公开(公告)日：2007-11-01

申请号：US11588319

申请日：2006-10-27

申请人： Naohiro Takahashi ,  Kiyoshi Irino

发明人： Naohiro Takahashi ,  Kiyoshi Irino

IPC分类号： G06F19/00 ,  G06F17/40

CPC分类号： G01N21/9501 ,  G01N21/9503

摘要： An inspecting method is capable of efficiently inspecting a wafer. According to the inspecting method, the chip area of a wafer is inspected for defects, and based on the results, a defect density D0p of each of peripheral-zone chips in the chip area which are located closely to the peripheral area of the wafer is calculated. A peripheral-zone chip with a high defect density D0p is selected, and an area in the peripheral area which is outward of the selected peripheral-zone chip is inspected for defects. Since only the area in the peripheral area which is located outward of the peripheral-zone chip selected based on the defect density D0p is inspected for defects, the wafer is inspected efficiently.

摘要翻译： 检查方法能够有效地检查晶片。 根据检查方法，检查晶片的芯片面积的缺陷，并且基于该结果，芯片区域中的每个周边区域芯片的缺陷密度D 0p 位于紧密的位置 计算晶圆的外围区域。 选择具有高缺陷密度D <0P 的周边区域芯片，并且检查在所选周边区域芯片外部的周边区域中的缺陷。 由于仅考虑了基于缺陷密度D 0p <0>的所选外围区域芯片周边区域的区域，故有效地检查晶片。

公开(公告)号：US06979658B2

公开(公告)日：2005-12-27

申请号：US09428052

申请日：1999-10-27

申请人： Kiyoshi Irino

发明人： Kiyoshi Irino

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/318 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/49 ,  H01L21/31

CPC分类号： H01L29/6659 ,  H01L21/28176 ,  H01L21/28194 ,  H01L27/10873 ,  H01L29/4983 ,  Y10S257/90

摘要： A semiconductor device includes a substrate, a gate oxide film formed on the substrate, a gate electrode provided on the gate oxide film, first and second diffusion regions formed in the substrate at both lateral sides of the gate electrode. The gate electrode includes a first region located immediately underneath the gate electrode and a second region adjacent to the first region, wherein the first and second regions contain N atoms with respective concentrations such that the second region contains N with a higher concentration as compared with the first region.

摘要翻译： 半导体器件包括衬底，形成在衬底上的栅极氧化膜，设置在栅极氧化膜上的栅电极，在栅电极的两个侧面处形成在衬底中的第一和第二扩散区。 所述栅电极包括位于所述栅电极正下方的第一区域和与所述第一区域相邻的第二区域，其中所述第一区域和所述第二区域包含具有各自浓度的N原子，使得所述第二区域与所述第一区域相比具有较高浓度的N 第一区。

公开(公告)号：US07005393B2

公开(公告)日：2006-02-28

申请号：US10170688

申请日：2002-06-14

申请人： Kiyoshi Irino

发明人： Kiyoshi Irino

IPC分类号： H01L21/31

CPC分类号： H01L29/6659 ,  H01L21/28176 ,  H01L21/28194 ,  H01L27/10873 ,  H01L29/4983 ,  Y10S257/90

摘要： A method of fabricating a semiconductor device which includes introducing, after a step of patterning a gate electrode, nitrogen atoms into an oxide film covering a device region on a semiconductor substrate, by exposing said oxide film to an atmosphere containing-nitrogen, such that said nitrogen atoms do not reach a region underneath said gate electrode, covering, after said step of introducing nitrogen atoms, said oxide film including said gate electrode by a CVD oxide film continuously without taking out said semiconductor substrate out of a processing chamber and forming a sidewall oxide film on a sidewall surface of said gate electrode by etching back said CVD oxide film.

摘要翻译： 一种半导体器件的制造方法，其特征在于，在通过将所述氧化物膜暴露在含氮的气氛中之后，将氮原子图案化的步骤引入到覆盖半导体衬底上的器件区域的氧化物膜中，使得所述 氮原子不到达所述栅电极下方的区域，在所述引入氮原子的步骤之后，连续地将所述包含所述栅电极的氧化膜通过CVD氧化膜覆盖，而不将所述半导体衬底从处理室中取出并形成侧壁 通过蚀刻所述CVD氧化物膜，在所述栅电极的侧壁表面上形成氧化膜。

公开(公告)号：US5990517A

公开(公告)日：1999-11-23

申请号：US917936

申请日：1997-08-27

申请人： Kiyoshi Irino

发明人： Kiyoshi Irino

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/318 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/49

CPC分类号： H01L29/6659 ,  H01L21/28176 ,  H01L29/4983 ,  H01L21/28194 ,  H01L27/10873 ,  Y10S257/90

摘要： A semiconductor device includes a substrate, a gate oxide film formed on the substrate, a gate electrode provided on the gate oxide film, first and second diffusion regions formed in the substrate at both lateral sides of the gate electrode. The gate electrode includes a first region located immediately underneath the gate electrode and a second region adjacent to the first region, wherein the first and second regions contain N atoms with respective concentrations such that the second region contains N with a higher concentration as compared with the first region.

摘要翻译： 半导体器件包括衬底，形成在衬底上的栅极氧化膜，设置在栅极氧化膜上的栅电极，在栅电极的两个侧面处形成在衬底中的第一和第二扩散区。 所述栅电极包括位于所述栅电极正下方的第一区域和与所述第一区域相邻的第二区域，其中所述第一区域和所述第二区域包含具有各自浓度的N原子，使得所述第二区域与所述第一区域相比具有较高浓度的N 第一区。

公开(公告)号：US06998303B2

公开(公告)日：2006-02-14

申请号：US10633534

申请日：2003-08-05

申请人： Yoshihiro Sugita ,  Yusuke Morisaki ,  Kiyoshi Irino ,  Shiqin Xiao ,  Takayuki Ohba

发明人： Yoshihiro Sugita ,  Yusuke Morisaki ,  Kiyoshi Irino ,  Shiqin Xiao ,  Takayuki Ohba

IPC分类号： H01L21/76

CPC分类号： H01L21/823857 ,  H01L21/265 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31122 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： An insulating film made of zirconia or hafnia is formed on the surface of a semiconductor substrate. A partial surface area of the insulating film is covered with a mask pattern. By using the mask pattern as a mask, ions are implanted into a region of the insulating film not covered with the mask pattern to give damages to the insulating film. By using the mask pattern as a mask, a portion of the insulating film is etched.

摘要翻译： 在半导体衬底的表面上形成由氧化锆或铪形成的绝缘膜。 绝缘膜的部分表面积被掩模图案覆盖。 通过使用掩模图案作为掩模，将离子注入到未被掩模图案覆盖的绝缘膜的区域中，以对绝缘膜造成损害。 通过使用掩模图案作为掩模，蚀刻绝缘膜的一部分。

公开(公告)号：US06468926B1

公开(公告)日：2002-10-22

申请号：US09342057

申请日：1999-06-29

申请人： Kiyoshi Irino ,  Ken-ichi Hikazutani ,  Tatsuya Kawamura ,  Taro Sugizaki ,  Satoshi Ohkubo ,  Toshiro Nakanishi ,  Kanetake Takasaki

发明人： Kiyoshi Irino ,  Ken-ichi Hikazutani ,  Tatsuya Kawamura ,  Taro Sugizaki ,  Satoshi Ohkubo ,  Toshiro Nakanishi ,  Kanetake Takasaki

IPC分类号： H01L2131

CPC分类号： H01L21/0214 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/31662

摘要： A manufacture method for a semiconductor device includes the steps of: (a) transporting a silicon wafer into a reaction chamber having first and second gas introducing inlet ports; (b) introducing an oxidizing atmosphere via the first gas introducing inlet port and raising the temperature of the silicon wafer to an oxidation temperature; (c) introducing a wet oxidizing atmosphere to form a thermal oxide film on the surface of the silicon wafer; (d) purging gas in the reaction chamber by using inert gas to lower a residual water concentration to about 1000 ppm or lower; and (e) introducing an NO or N2O containing atmosphere into the reaction chamber via the second gas introducing inlet port while the silicon wafer is maintained above 700° C. and above the oxidation temperature, to introduce nitrogen into the thermal oxide film and form an oxynitride film. A thin oxynitride film can be manufactured with good mass productivity.

摘要翻译： 半导体器件的制造方法包括以下步骤：（a）将硅晶片输送到具有第一和第二气体引入入口的反应室中; （b）经由第一气体导入口引入氧化气氛，将硅晶片的温度升高至氧化温度; （c）引入湿氧化气氛以在硅晶片的表面上形成热氧化膜; （d）通过使用惰性气体将残留水浓度降低至约1000ppm或更低，在反应室中吹扫气体; 和（e）在硅晶片保持在700℃以上并高于氧化温度的同时，经由第二气体导入口将NO或N 2 O的气氛引入反应室，将氮引入热氧化膜中，形成 氧氮化物膜。 可以以良好的质量生产率制造薄氧氮化物膜。

公开(公告)号：US06984267B2

公开(公告)日：2006-01-10

申请号：US10235824

申请日：2002-09-06

申请人： Kiyoshi Irino ,  Ken-ichi Hikazutani ,  Tatsuya Kawamura ,  Taro Sugizaki ,  Satoshi Ohkubo ,  Toshiro Nakanishi ,  Kanetake Takasaki

发明人： Kiyoshi Irino ,  Ken-ichi Hikazutani ,  Tatsuya Kawamura ,  Taro Sugizaki ,  Satoshi Ohkubo ,  Toshiro Nakanishi ,  Kanetake Takasaki

IPC分类号： C23C16/00 ,  F27D3/12

CPC分类号： H01L21/0214 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/31662

摘要： A manufacture method for a semiconductor device includes the steps of: (a) transporting a silicon wafer into a reaction chamber having first and second gas introducing inlet ports; (b) introducing an oxidizing atmosphere via the first gas introducing inlet port and raising the temperature of the silicon wafer to an oxidation temperature; (c) introducing a wet oxidizing atmosphere to form a thermal oxide film on the surface of the silicon wafer; (d) purging gas in the reaction chamber by using inert gas to lower a residual water concentration to about 1000 ppm or lower; and (e) introducing an NO or N2O containing atmosphere into the reaction chamber via the second gas introducing inlet port while the silicon wafer is maintained above 700° C. and above the oxidation temperature, to introduce nitrogen into the thermal oxide film and form an oxynitride film. A thin oxynitride film can be manufactured with good mass productivity.

摘要翻译： 半导体器件的制造方法包括以下步骤：（a）将硅晶片输送到具有第一和第二气体引入入口的反应室中; （b）经由第一气体导入口引入氧化气氛，将硅晶片的温度升高至氧化温度; （c）引入湿氧化气氛以在硅晶片的表面上形成热氧化膜; （d）通过使用惰性气体将残留水浓度降低至约1000ppm或更低，在反应室中吹扫气体; 和（e）通过第二气体引入入口将含有NO或N 2 O 2的气氛引入反应室，同时将硅晶片保持在700℃以上并高于氧化温度，以引入 氮气进入热氧化膜并形成氧氮化物膜。 可以以良好的质量生产率制造薄氧氮化物膜。

公开(公告)号：US06894369B2

公开(公告)日：2005-05-17

申请号：US10109001

申请日：2002-03-29

申请人： Kiyoshi Irino ,  Yusuke Morisaki ,  Yoshihiro Sugita ,  Yoshiaki Tanida ,  Yoshihisa Iba

发明人： Kiyoshi Irino ,  Yusuke Morisaki ,  Yoshihiro Sugita ,  Yoshiaki Tanida ,  Yoshihisa Iba

IPC分类号： H01L29/78 ,  C23C16/30 ,  C23C16/44 ,  C23C16/455 ,  H01L21/28 ,  H01L21/314 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/51 ,  H01L23/58

CPC分类号： H01L21/28194 ,  C23C16/308 ,  C23C16/45525 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/3144 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/517 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ultra high-speed semiconductor device has a high-K dielectric gate insulator layer, wherein spread of impurities to a Si substrate from a gate electrode through the high-K dielectric gate insulator layer, and spread of oxygen and metallic elements from the high-K dielectric gate insulator layer to the Si substrate or the gate electrode are suppressed by arranging the high-K dielectric film sandwiched by nitrogen atomic layers on the Si substrate that is covered by an oxygen atomic layer.

摘要翻译： 超高速半导体器件具有高K电介质栅极绝缘体层，其中通过高K电介质栅极绝缘体层从栅电极向Si衬底扩散杂质，并且从高电介质栅极绝缘体层扩散氧和金属元素， 通过在被氧原子层覆盖的Si衬底上布置由氮原子层夹持的高K电介质膜来抑制Si衬底或栅电极的K介质栅极绝缘体层。