公开(公告)号：US07915655B2

公开(公告)日：2011-03-29

申请号：US12056603

申请日：2008-03-27

申请人： Naohiro Ueda

发明人： Naohiro Ueda

IPC分类号： H01L27/108

CPC分类号： H01L21/823418 ,  H01L27/088 ,  H01L29/42324 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes a semiconductor substrate and a metal-oxide semiconductor transistor. A first dielectric layer of the metal oxide semiconductor transistor overlaps source and drain electrodes and a channel region of the transistor. A first drain region is away from the channel region and the first dielectric layer. A second drain region is between the first drain region and the channel region. A gate electrode is on the first dielectric layer and connected to a gate wire, and includes first and second gate layers and a dielectric layer therebetween. The first gate layer has one edge laterally spaced from the first drain region and resting over the second drain region, and is isolated from the gate wire. The second gate layer is over the first gate layer and is connected to the gate wire.

摘要翻译： 半导体器件包括半导体衬底和金属氧化物半导体晶体管。 金属氧化物半导体晶体管的第一电介质层与源极和漏极以及晶体管的沟道区重叠。 第一漏极区域远离沟道区域和第一介电层。 第二漏区在第一漏区和沟道区之间。 栅电极位于第一电介质层上并连接到栅极线，并且包括第一和第二栅极层和介电层之间。 第一栅极层具有与第一漏极区域横向间隔开并且搁置在第二漏极区域上的一个边缘，并且与栅极线隔离。 第二栅极层在第一栅极层上方并且连接到栅极线。

公开(公告)号：US07755195B2

公开(公告)日：2010-07-13

申请号：US11517781

申请日：2006-09-08

申请人： Naohiro Ueda

发明人： Naohiro Ueda

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/45099

摘要： A semiconductor apparatus includes a device, two metal-wiring layers, and an insulation film. The device includes first and second electrodes. The two metal-wiring layers include uppermost and next-uppermost metal-wiring layers. The insulation film is formed on the uppermost metal-wiring layer and includes first and second pad openings. The uppermost metal-wiring layer has a first portion exposed to air through the first pad opening and forming a first electrode pad, and the uppermost metal-wiring layer has a second portion exposed to air through the second pad opening and forming a second electrode pad. The first and second electrode pads are located over the device and are electrically connected to the first and second electrodes, respectively. The next-uppermost metal-wiring layer has a first portion located under the first electrode pad and electrically connected thereto, and a second portion located under the second electrode pad and electrically connected thereto.

摘要翻译： 半导体装置包括器件，两个金属布线层和绝缘膜。 该装置包括第一和第二电极。 两个金属布线层包括最上面和下一个最上层的金属布线层。 绝缘膜形成在最上层的金属布线层上，并且包括第一和第二焊盘开口。 最上面的金属布线层具有通过第一焊盘开口暴露于空气的第一部分，并形成第一电极焊盘，最上面的金属布线层具有通过第二焊盘开口暴露于空气的第二部分，并形成第二电极焊盘 。 第一和第二电极焊盘位于器件上方并分别与第一和第二电极电连接。 下一个最上层的金属布线层具有位于第一电极焊盘下方并与之电连接的第一部分，以及位于第二电极焊盘下方并与之电连接的第二部分。

公开(公告)号：US07084035B2

公开(公告)日：2006-08-01

申请号：US11104433

申请日：2005-04-13

申请人： Naohiro Ueda

发明人： Naohiro Ueda

IPC分类号： H01L21/8234

CPC分类号： H01L27/0629 ,  H01L21/82345 ,  H01L21/823462 ,  Y10S438/981

摘要： A method for forming three kinds of MOS transistors on a single semiconductor substrate, each provided with gate oxides different in thickness from each other, without detracting from the device characteristics. The method includes the steps of forming a dielectric layer for device isolation for defining first, second, and third regions, and buffer oxide layers on the surface of a semiconductor substrate; after forming an oxidation resistance layer, which has an opening for exposing the first region, performing a first thermal oxidation process for forming a first gate oxide layer overlaying the first region; forming a first gate electrode on the first gate oxide layer; removing the buffer oxide layer overlying the third region, having an opening for exposing the third region; performing a second thermal oxidation process for forming a second gate oxide layer, having a thickness different from the first gate oxide, and for forming a third gate oxide layer having a thickness different from the first, and the second gate oxides.

摘要翻译： 一种用于在单个半导体衬底上形成三种MOS晶体管的方法，每个半导体衬底均设置有彼此不同厚度的栅极氧化物，而不会降低器件特性。 该方法包括以下步骤：在半导体衬底的表面上形成用于器件隔离的介电层，用于限定第一，第二和第三区域以及缓冲氧化物层; 在形成具有用于暴露第一区域的开口的抗氧化层之后，进行用于形成覆盖第一区域的第一栅极氧化物层的第一热氧化工艺; 在所述第一栅极氧化物层上形成第一栅电极; 去除覆盖在第三区域上的缓冲氧化物层，具有用于暴露第三区域的开口; 进行第二热氧化工艺以形成具有不同于第一栅极氧化物的厚度的第二栅极氧化物层，以及用于形成具有不同于第一栅极氧化物的厚度的第三栅极氧化物层。

公开(公告)号：US06917081B2

公开(公告)日：2005-07-12

申请号：US10422786

申请日：2003-04-25

申请人： Naohiro Ueda ,  Yoshinori Ueda

发明人： Naohiro Ueda ,  Yoshinori Ueda

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/76

CPC分类号： H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/0928

摘要： A semiconductor device is provided comprising several device components formed in the same substrate, such as a P-substrate having an offset Nch transistor including N-type source and drain each formed in a P-well spatially separated from one another, and the drain surrounded by a low concentration N-type diffusion layer; an offset Pch transistor including P-type source and drain each formed in an N-well spatially separated from one another, and the drain surrounded by a low concentration P-type diffusion layer; a triple well including a deep N-well, and a P-type IP well formed therein; a normal N-well for forming a Pch MOS transistor; and a normal P-well for forming an Nch MOS transistor; in which simultaneously formed are the low concentration N-type diffusion layer, N-well and normal N-well; the P-well and normal P-well; and the low concentration P-type diffusion layer and IP well.

摘要翻译： 提供了一种半导体器件，其包括形成在同一衬底中的若干器件组件，例如具有偏置N沟道晶体管的P衬底，其中N型晶体管包括N型源极和漏极，其各自形成在彼此空间上分离的P阱中，并且漏极包围 通过低浓度N型扩散层; 偏移Pch晶体管，包括P型源极和漏极，各自形成在空间上彼此分离的N阱中，并且由低浓度P型扩散层包围的漏极; 包括深N阱的三阱和在其中形成的P型IP阱; 用于形成Pch MOS晶体管的正常N阱; 以及用于形成Nch MOS晶体管的正常P阱; 其中同时形成低浓度N型扩散层，N阱和正常N阱; P井和正常P井; 和低浓度P型扩散层和IP井。

公开(公告)号：US08716874B2

公开(公告)日：2014-05-06

申请号：US13228583

申请日：2011-09-09

申请人： Junichi Konishi ,  Naohiro Ueda

发明人： Junichi Konishi ,  Naohiro Ueda

IPC分类号： H01L29/40

CPC分类号： H01L27/0207 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/061 ,  H01L2224/0612 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device that is resin-sealed in a wafer level after a rewiring layer forming process and a metal post forming process forming a metal post are performed on a semiconductor substrate of the semiconductor device includes devices formed on the semiconductor substrate. Further all of the devices are disposed in respective positions other than positions overlapping a peripheral border of the metal post when viewed from a top of the semiconductor substrate.

摘要翻译： 在半导体器件的半导体衬底上，在重新布线层形成工艺和形成金属柱的金属柱形成工艺之后，在晶片级树脂密封的半导体器件包括在半导体衬底上形成的器件。 此外，当从半导体衬底的顶部观察时，所有器件都设置在与金属柱的外围边界重叠的位置以外的各个位置。

公开(公告)号：US07934429B2

公开(公告)日：2011-05-03

申请号：US12758549

申请日：2010-04-12

申请人： Naohiro Ueda ,  Hirofumi Watanabe

发明人： Naohiro Ueda ,  Hirofumi Watanabe

IPC分类号： G01B7/16

CPC分类号： G01L1/16 ,  G01L1/2293 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A stress-distribution detecting semiconductor package group includes multiple stress-distribution detecting semiconductor packages each formed by resin-encapsulating a stress detecting semiconductor chip of the same size using an identical resin encapsulation structure. Each stress detecting semiconductor chip includes a piezoelectric element for stress detection and at least two electrode pads electrically connected to the piezoelectric element to measure an electrical property of the piezoelectric element. The piezoelectric elements of the stress detecting semiconductor chips are respectively disposed on the corresponding stress detecting semiconductor chips to be located at different positions from one another.

摘要翻译： 应力分布检测半导体封装组包括通过使用相同的树脂封装结构树脂封装相同尺寸的应力检测半导体芯片而形成的多个应力分布检测半导体封装。 每个应力检测半导体芯片包括用于应力检测的压电元件和与压电元件电连接以测量压电元件的电性能的至少两个电极焊盘。 应力检测半导体芯片的压电元件分别设置在相应的应力检测半导体芯片上，以位于彼此不同的位置。

公开(公告)号：US20090064791A1

公开(公告)日：2009-03-12

申请号：US12201350

申请日：2008-08-29

申请人： Naohiro Ueda ,  Hirofumi Watanabe

发明人： Naohiro Ueda ,  Hirofumi Watanabe

IPC分类号： G01B7/16

CPC分类号： G01L1/16 ,  G01L1/2293 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A disclosed stress-distribution detecting semiconductor package group includes multiple stress-distribution detecting semiconductor packages each formed by resin-encapsulating a stress detecting semiconductor chip of the same size using an identical resin encapsulation structure. Each stress detecting semiconductor chip includes a piezoelectric element for stress detection and at least two electrode pads electrically connected to the piezoelectric element to measure an electrical property of the piezoelectric element. The piezoelectric elements of the stress detecting semiconductor chips are respectively disposed on the corresponding stress detecting semiconductor chips to be located at different positions from one another when superimposed on a single imaginary semiconductor chip plane having the same plane size as that of the stress detecting semiconductor chips.

摘要翻译： 所公开的应力分布检测半导体封装组包括通过使用相同的树脂封装结构树脂密封相同尺寸的应力检测半导体芯片而形成的多个应力分布检测半导体封装。 每个应力检测半导体芯片包括用于应力检测的压电元件和与压电元件电连接以测量压电元件的电性能的至少两个电极焊盘。 应力检测半导体芯片的压电元件分别设置在相应的应力检测半导体芯片上，以在叠加在具有与应力检测半导体芯片相同的平面尺寸的单个虚拟半导体芯片平面上时彼此不同的位置 。

公开(公告)号：US20090050978A1

公开(公告)日：2009-02-26

申请号：US11914872

申请日：2007-03-12

申请人： Naohiro Ueda

发明人： Naohiro Ueda

IPC分类号： H01L27/088

CPC分类号： H01L29/78 ,  H01L27/088

摘要： A disclosed semiconductor device includes a driver transistor including a source and a drain of a second conductive type provided with an interval therebetween in a semiconductor substrate of a first conductive type, a gate electrode extending in a predetermined direction and provided on the semiconductor substrate via a gate insulating film between the source and the drain, plural insular back gate diffusion layers of the first conductive type provided in the source so as to be in contact with the semiconductor substrate, wherein the back gate diffusion layers are spaced apart and arranged in the predetermined direction in the source, and a contact hole extending in the predetermined direction on the source and at least one of the back gate diffusion layers.

摘要翻译： 所公开的半导体器件包括驱动晶体管，其包括在第一导电类型的半导体衬底中设置有间隔的第二导电类型的源极和漏极，沿预定方向延伸的栅电极，并且经由 源极和漏极之间的栅极绝缘膜，设置在源极中的第一导电类型的多个岛状后栅极扩散层以与半导体衬底接触，其中后栅极扩散层间隔开并布置成预定的 在源极上的方向，以及在源极和至少一个背栅扩散层上沿预定方向延伸的接触孔。

公开(公告)号：US20050221551A1

公开(公告)日：2005-10-06

申请号：US11134386

申请日：2005-05-23

申请人： Naohiro Ueda ,  Yoshinori Ueda

发明人： Naohiro Ueda ,  Yoshinori Ueda

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/0928

摘要： A semiconductor device is provided comprising several device components formed in the same substrate, such as a P-substrate having an offset Nch transistor including N-type source and drain each formed in a P-well spatially separated from one another, and the drain surrounded by a low concentration N-type diffusion layer; an offset Pch transistor including P-type source and drain each formed in an N-well spatially separated from one another, and the drain surrounded by a low concentration P-type diffusion layer; a triple well including a deep N-well, and a P-type IP well formed therein; a normal N-well for forming a Pch MOS transistor; and a normal P-well for forming an Nch MOS transistor; in which simultaneously formed are the low concentration N-type diffusion layer, N-well and normal N-well; the P-well and normal P-well; and the low concentration P-type diffusion layer and IP well.

摘要翻译： 提供了一种半导体器件，其包括形成在同一衬底中的若干器件组件，例如具有偏置N沟道晶体管的P衬底，其中N型晶体管包括N型源极和漏极，其各自形成在彼此空间上分离的P阱中，并且漏极包围 通过低浓度N型扩散层; 偏移Pch晶体管，包括P型源极和漏极，各自形成在空间上彼此分离的N阱中，并且由低浓度P型扩散层包围的漏极; 包括深N阱的三阱和在其中形成的P型IP阱; 用于形成Pch MOS晶体管的正常N阱; 以及用于形成Nch MOS晶体管的正常P阱; 其中同时形成低浓度N型扩散层，N阱和正常N阱; P井和正常P井; 和低浓度P型扩散层和IP井。

公开(公告)号：US20100193887A1

公开(公告)日：2010-08-05

申请号：US12758549

申请日：2010-04-12

申请人： Naohiro Ueda ,  Hirofumi Watanabe

发明人： Naohiro Ueda ,  Hirofumi Watanabe

IPC分类号： H01L29/84

CPC分类号： G01L1/16 ,  G01L1/2293 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A disclosed stress-distribution detecting semiconductor package group includes multiple stress-distribution detecting semiconductor packages each formed by resin-encapsulating a stress detecting semiconductor chip of the same size using an identical resin encapsulation structure. Each stress detecting semiconductor chip includes a piezoelectric element for stress detection and at least two electrode pads electrically connected to the piezoelectric element to measure an electrical property of the piezoelectric element. The piezoelectric elements of the stress detecting semiconductor chips are respectively disposed on the corresponding stress detecting semiconductor chips to be located at different positions from one another when superimposed on a single imaginary semiconductor chip plane having the same plane size as that of the stress detecting semiconductor chips.

摘要翻译： 所公开的应力分布检测半导体封装组包括通过使用相同的树脂封装结构树脂密封相同尺寸的应力检测半导体芯片而形成的多个应力分布检测半导体封装。 每个应力检测半导体芯片包括用于应力检测的压电元件和与压电元件电连接以测量压电元件的电性能的至少两个电极焊盘。 应力检测半导体芯片的压电元件分别设置在相应的应力检测半导体芯片上，以在叠加在具有与应力检测半导体芯片相同的平面尺寸的单个虚拟半导体芯片平面上时彼此不同的位置 。