公开(公告)号：US4196440A

公开(公告)日：1980-04-01

申请号：US909338

申请日：1978-05-25

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  Hans B. Pogge

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  Hans B. Pogge

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/08 ,  H01L29/735 ,  H01L29/06

CPC分类号： H01L27/0821 ,  H01L21/76232 ,  H01L29/735 ,  Y10S148/031 ,  Y10S148/051 ,  Y10S148/085

摘要： Lateral PNP or NPN devices in isolated monocrystalline silicon pockets wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline region are described. The P emitter or N emitter diffusion is made over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket. This structure reduces the vertical current injection which will give relatively high (beta) gain even at low base to emitter voltages.

摘要翻译： 描述了分离的单晶硅袋中的侧向PNP或NPN器件，其中二氧化硅隔离围绕该口袋并且部分地在该表面之下在隔离的单晶区域内。 P发射体或N发射体扩散在部分延伸到单晶隔离袋中的二氧化硅部分上进行。 这种结构减少了垂直电流注入，即使在低的基极 - 发射极电压下也将提供相对较高的（β）增益。

公开(公告)号：US4691435A

公开(公告)日：1987-09-08

申请号：US263227

申请日：1981-05-13

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  John L. Mauer, IV

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  John L. Mauer, IV

IPC分类号： H01L29/47 ,  H01L29/872 ,  H01L21/385

CPC分类号： H01L29/872

摘要： A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.

摘要翻译： 公开了用于在肖特基势垒二极管中制造小面积自对准保护环的方法。 垂直壁孔通过硅衬底上的电介质层完全各向异性地蚀刻。 掺杂多晶硅层沉积在有孔介电层上。 多晶硅被反射离子蚀刻掉，仅留下围绕电介质层中孔周边的衬里。 该结构被加热以将掺杂剂从衬里扩散到衬底中。 肖特基二极管金属沉积在通过介电层中的衬里孔暴露的衬底上。

公开(公告)号：US4427989A

公开(公告)日：1984-01-24

申请号：US293546

申请日：1981-08-14

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  James L. Walsh

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  James L. Walsh

IPC分类号： G11C11/41 ,  G11C11/34 ,  G11C11/401 ,  H01L21/8229 ,  H01L27/102 ,  H01L27/115 ,  H01L29/74

CPC分类号： H01L27/1023 ,  G11C11/34 ,  H01L27/1028 ,  H01L27/115

摘要： A dynamic memory cell has a P+ injector region surrounded by an N+ region in an N- layer on an N+ layer. The injector region is placed between N+ source and drain regions. Holes injected into the N-layer are trapped by the high-low junctions at the N+, N- interfaces and are detected by sensing the source-drain current. Current levels are used to establish binary one and zero levels in the cell. Four masks in an aligned procedure simplify fabrication.

摘要翻译： 动态存储单元具有由N +层上的N层中的N +区包围的P +注入区。 喷射器区域放置在N +源极和漏极区域之间。 注入N层的孔被N +，N-界面处的高低接头捕获，并通过感测源极 - 漏极电流来检测。 当前级别用于在单元格中建立二进制一和零级。 对齐程序中的四个掩模简化了制造。

公开(公告)号：US4796069A

公开(公告)日：1989-01-03

申请号：US63345

申请日：1987-06-18

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  John L. Mauer, IV

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  John L. Mauer, IV

IPC分类号： H01L29/872 ,  H01L29/48 ,  H01L29/04 ,  H01L29/34

CPC分类号： H01L29/872

摘要： A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.

摘要翻译： 公开了用于在肖特基势垒二极管中制造小面积自对准保护环的方法。 垂直壁孔通过硅衬底上的电介质层完全各向异性地蚀刻。 掺杂多晶硅层沉积在有孔介电层上。 多晶硅被反射离子蚀刻掉，仅留下围绕电介质层中孔周边的衬里。 该结构被加热以将掺杂剂从衬里扩散到衬底中。 肖特基二极管金属沉积在通过介电层中的衬里孔暴露的衬底上。

公开(公告)号：US4264382A

公开(公告)日：1981-04-28

申请号：US84213

申请日：1979-10-12

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Caur ,  Hans B. Pogge

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Caur ,  Hans B. Pogge

IPC分类号： H01L21/3065 ,  H01L21/762 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/735 ,  H01L21/22 ,  H01L21/467 ,  H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/3065 ,  H01L21/8224 ,  H01L27/0821 ,  H01L29/735

摘要： A method for making lateral PNP or NPN devices in isolated monocrystalline silicon pockets wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline region. The P emitter or N emitter diffusion is made over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket. This structure reduces the vertical current injection which will give relatively high (beta) gain even at low base to emitter voltages. The lateral PNP or NPN device resulting from the method is in a monocrystalline silicon pocket wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline silicon region. The P emitter or N emitter diffusion is located over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket.

摘要翻译： 在隔离的单晶硅袋中制造横向PNP或NPN器件的方法，其中二氧化硅隔离围绕在孤立的单晶区域内的口袋和部分地在表面下方。 P发射体或N发射体扩散在部分延伸到单晶隔离袋中的二氧化硅部分上进行。 这种结构减少了垂直电流注入，即使在低的基极 - 发射极电压下也将提供相对较高的（β）增益。 由该方法产生的横向PNP或NPN器件是在单晶硅袋中，其中二氧化硅隔离围绕在隔离的单晶硅区域内的口袋和部分地在表面下方。 P发射极或N发射极扩散位于部分延伸到单晶隔离袋中的二氧化硅部分之上。

公开(公告)号：US4389281A

公开(公告)日：1983-06-21

申请号：US217077

申请日：1980-12-16

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  John S. Lechaton ,  James L. Walsh

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  John S. Lechaton ,  James L. Walsh

IPC分类号： C01B33/12 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/312 ,  H01L21/76 ,  H01L21/306 ,  C03C15/00

CPC分类号： H01L21/31055 ,  H01L21/31116 ,  H01L21/312

摘要： The present invention provides a method for planarizing a non-uniform thickness of oxide, for example silicon dioxide as is formed over oxide-filled trenches used in deep dielectric isolation in integrated circuits. The oxide is removed by a planarizing resist-etching process so that etching in thicker resist areas proceeds at a rate slower than etching in thinner resist areas. A referred etchant is HF gas and etching is preferably at an elevated temperature.

摘要翻译： 本发明提供了一种平面化不均匀厚度的氧化物的方法，例如在集成电路中用于深介电隔离的氧化物填充沟槽上形成的二氧化硅。 通过平面化抗蚀剂蚀刻工艺去除氧化物，使得较厚抗蚀剂区域中的蚀刻以比较薄的抗蚀剂区域中的蚀刻速率慢。 所谓蚀刻剂是HF气体，蚀刻优选处于升高的温度。

公开(公告)号：US4389294A

公开(公告)日：1983-06-21

申请号：US279129

申请日：1981-06-30

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  John L. Mauer, IV ,  Homi G. Sarkary

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  John L. Mauer, IV ,  Homi G. Sarkary

IPC分类号： H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  C23C15/00

CPC分类号： H01L21/76224 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76202 ,  Y10S438/978

摘要： A method for eliminating deposited residues, for example polysilicon residue, on vertical silicon dioxide sidewalls that have been reactive ion etched includes reshaping the sidewalls to have a slope of at least +30.degree. relative to the vertical direction of the sidewall.

摘要翻译： 用于消除已经被反应离子蚀刻的垂直二氧化硅侧壁上沉积的残留物（例如多晶硅残余物）的方法包括使侧壁重新形成相对于侧壁的垂直方向具有至少+ 30°的斜率。

公开(公告)号：UST101201I4

公开(公告)日：1981-11-03

申请号：US254039

申请日：1981-04-14

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia

IPC分类号： H01L21/033 ,  H01L21/3205 ,  H01L21/60 ,  H01L29/47 ,  H01L29/872

CPC分类号： H01L21/76897 ,  H01L21/0337 ,  H01L21/32051 ,  H01L29/475 ,  H01L29/872

摘要： Excessive leakage after initial forward stress, exhibited by subsequently reverse stressed nitride defined, Schottky barrier diodes is solved by the elimination of the "mouse hole" or undercut cavity in the oxide layer beneath the nitride ring defining the Schottky contact to the underlying silicon. The aforementioned cavity is filled by depositing chemical vapor deposited (CVD) oxide onto the nitride layer, into the nitride ring and the undercut oxide cavity beneath the ring and onto the underlying silicon substrate exposed through the nitride ring. The CVD oxide is then reactively ion etched to remove it except along the vertical walls of the nitride ring and the oxide cavity. The Schottky metal is deposited on the silicon substrate exposed by the reactive ion etching step.

公开(公告)号：US4159915A

公开(公告)日：1979-07-03

申请号：US844767

申请日：1977-10-25

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  James L. Walsh

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  James L. Walsh

IPC分类号： H01L21/76 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/06 ,  H01L27/07 ,  H01L27/082 ,  H01L29/06 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L29/0649 ,  H01L21/743 ,  H01L21/82285 ,  H01L27/0755 ,  H01L27/0826 ,  H01L27/0828 ,  Y10S148/131

摘要： A method is given for fabricating vertical NPN and PNP structures on the same semiconductor body. The method involves providing a monocrystalline semiconductor substrate having regions of monocrystalline silicon isolated from one another by isolation regions. Buried regions are formed overlapping the juncture of the substrate and epitaxial layer and are located in at least one of the regions of isolated monocrystalline silicon. The P base region in the NPN designated regions and a P reach-through in the PNP designated regions are formed simultaneously. The emitter region in the NPN regions and base contact region in the PNP regions are then formed simultaneously. The P emitter region in the PNP regions is then implanted by suitable ion implantation techniques. A Schottky Barrier collector contact in the PNP regions are formed. Electrical contacts are then made to the PNP and NPN transistor elements. A PNP device may be fabricated without the formation of an NPN device if it is so desired.

摘要翻译： 给出了在同一半导体器件上制造垂直NPN和PNP结构的方法。 该方法包括提供具有通过隔离区彼此隔离的单晶硅区域的单晶半导体衬底。 掩埋区域形成为与衬底和外延层的接合部重叠，并且位于分离的单晶硅的至少一个区域中。 NPN指定区域中的P基区域和PNP指定区域中的P到达通孔同时形成。 然后在NPN区域中的发射极区域和PNP区域中的基极接触区域同时形成。 然后通过合适的离子注入技术注入PNP区域中的P发射极区域。 形成PNP区域中的肖特基势垒集电极触点。 然后对PNP和NPN晶体管元件进行电触点。 如果需要，可以制造PNP器件而不形成NPN器件。

公开(公告)号：US4236294A

公开(公告)日：1980-12-02

申请号：US21124

申请日：1979-03-16

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  James L. Walsh

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  James L. Walsh

IPC分类号： H01L21/033 ,  H01L21/321 ,  H01L23/532 ,  B01J17/00

CPC分类号： H01L23/53271 ,  H01L21/033 ,  H01L21/321 ,  H01L2924/0002 ,  Y10S148/131

摘要： A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base regions.

摘要翻译： 描述了一种用于制造高性能双极器件的方法和所得到的具有非常小的发射极 - 基极间距的结构。 与较早的器件间隔相比，小的发射极 - 基极间距降低了基极电阻，从而提高了双极器件的性能。 该方法包括提供具有通过隔离区域彼此隔离的单晶硅区域的硅半导体本体和其中的掩埋子集电极。 在分离的单晶硅中形成基极区。 在覆盖指定为发射极和集电极到达区域的区域的硅体的表面上形成掩模。 然后通过覆盖基极区域的掩模形成掺杂的多晶硅层，并与其形成欧姆接触。 在多晶硅层上形成绝缘层。 从指定为发射极和集电极到达区域的区域中去除掩模。 然后在基极区域中形成发射极结，并且集电极通过形成为与掩埋的子集电极接触。 电触点被制成发射极和集电极。 掺杂多晶硅层是与基极区的电接触。