公开(公告)号：US20140264271A1

公开(公告)日：2014-09-18

申请号：US13845366

申请日：2013-03-18

Applicant: NATIONAL APPLIED RESEARCH LABORATORIES

Inventor： Jia-Min Shieh ,  Wen-Hsien Huang ,  Yu-Chung Lien ,  Chang-Hong Shen ,  Fu-Ming Pan ,  Hao-Chung Kuo

IPC: H01L29/15 ,  H01L29/06

CPC classification number: H01L29/0665 ,  C04B35/14 ,  C04B35/62218 ,  C04B35/624 ,  C04B38/0054 ,  C04B2235/3224 ,  C04B2235/443 ,  C04B2235/616 ,  C04B2235/9646 ,  G11C11/221

Abstract: A ferroelectric memory device includes a memory layer, made of a silicon-based ferroelectric memory material. The silicon-based ferroelectric memory material includes a mesoporous silica film with nanopores and atomic polar structures on inner walls of the nanopores. The atomic polar structures are formed by asymmetrically bonding metal ions to silicon-oxygen atoms on the inner walls, and the silicon-based ferroelectric memory material includes semiconductor quantum dots, metal quantum dots and metal-semiconductor alloy quantum dots.

Abstract translation: 铁电存储器件包括由硅基铁电存储材料制成的存储层。 硅基铁电记忆材料包括具有纳米孔的介孔二氧化硅膜和在纳米孔的内壁上的原子极性结构。 原子极性结构通过将金属离子与内壁上的硅 - 氧原子不对称地结合而形成，硅基铁电存储材料包括半导体量子点，金属量子点和金属 - 半导体合金量子点。

公开(公告)号：US11415457B2

公开(公告)日：2022-08-16

申请号：US16170471

申请日：2018-10-25

Applicant: NATIONAL APPLIED RESEARCH LABORATORIES

Inventor： Yu-Sheng Lai ,  Jui-Min Liu ,  Hsu-Chun Cheng ,  Mei-I Li ,  Chun-Chi Chen ,  Cheng-San Wu ,  Jia-Min Shieh

IPC: G01H11/02

Abstract: The present invention provides a vibration sensor, which comprises a circuit board having an accommodating space. A sensing assembly is disposed in the accommodating space. A recess for magnet sliding is disposed in the sensing assembly. Dispose a magnet in the recess and then dispose a coil layer on an arbitrary side or both sides of the sensing assembly. Furthermore, a lubricating layer is coated on the recess. Alternatively, the recess can be a vacuum structure or a hollow cross-sectional structure for reducing the friction between the recess and the magnet. Alternatively, the coil layer can be coated with a protective layer or multiple layers can be stacked. Without increasing the area of the sensor, the sensing on the variation of magnetic flux can be improved. Accordingly, the vibration sensor according to the present invention can achieve wideband detection of vibrations.

公开(公告)号：US10533962B2

公开(公告)日：2020-01-14

申请号：US15370384

申请日：2016-12-06

Applicant: NATIONAL APPLIED RESEARCH LABORATORIES

Inventor： Yu-Jen Hsiao ,  Ting-Jen Hsueh ,  Yu-Te Lin ,  Yen-Hsi Li ,  Jia-Min Shieh ,  Chien-Wei Liu ,  Chi-Wei Chiang

IPC: G01N27/12 ,  G01N33/00

Abstract: The present invention provides a gas sensor structure comprising a gas sensing chip. The back of the sensing material is a hollow structure. An insulating layer is below the sensing material. A micro heating is disposed surrounding the sensing material. The sensing material adheres to sensing electrodes. The sensing material is a complex structure including a metal oxide semiconductor and a roughened lanthanum-carbonate gas sensing layer. The thickness of the metal oxide semiconductor is between 0.2 μm and 10 μm; the thickness of the roughened lanthanum-carbonate gas sensing layer is between 0.1 μm and 4 μm; and the size of the back etching holes is smaller than 1*1 mm. By using the gas sensor structure according to the present invention, a suspended gas sensing structure can be fabricated on a silicon substrate and the chip size can be minimized.

公开(公告)号：US20140131716A1

公开(公告)日：2014-05-15

申请号：US13744594

申请日：2013-01-18

Applicant: NATIONAL APPLIED RESEARCH LABORATORIES

Inventor： Jia-Min Shieh ,  Yu-Chung Lien ,  Wen-Hsien Huang ,  Chang-Hong Shen ,  Min-Cheng Chen ,  Ci-Ling Pan

IPC: H01L29/792

CPC classification number: H01L29/66825 ,  B82Y40/00 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/7881 ,  Y10S977/774

Abstract: A memory device comprises a substrate, a tunnel oxide layer, a charge trapping layer, a block oxide layer, a plurality of conductive quantum dots, a metal gate and a source/drain structure. The tunnel oxide layer is disposed on the substrate and has a thickness substantially less than or equal to 2 nm. The charge trapping layer is disposed on the tunnel oxide layer. The quantum dots are embedded in the charge trapping layer. The block oxide layer is disposed on the charge trapping layer. The metal gate essentially consisting of aluminum (Al), copper (Cu), tantalum nitride (TiN), titanium nitride (TaN), aluminum-silicon-copper (Al—Si—Cu) alloys or the arbitrary combinations thereof is disposed on the block oxide layer. The source/drain structure is disposed in the substrate.

Abstract translation: 存储器件包括衬底，隧道氧化物层，电荷俘获层，块状氧化物层，多个导电量子点，金属栅极和源极/漏极结构。 隧道氧化物层设置在基板上，其厚度基本上小于或等于2nm。 电荷捕获层设置在隧道氧化物层上。 量子点嵌入电荷俘获层中。 块状氧化物层设置在电荷俘获层上。 基本上由铝（Al），铜（Cu），氮化钽（TiN），氮化钛（TaN），铝 - 硅 - 铜（Al-Si-Cu）合金或其任意组合组成的金属栅极设置在 块状氧化物层。 源极/漏极结构设置在衬底中。

公开(公告)号：US10656129B2

公开(公告)日：2020-05-19

申请号：US15837227

申请日：2017-12-11

Applicant: NATIONAL APPLIED RESEARCH LABORATORIES

Inventor： Ting-Jen Hsueh ,  Yu-Jen Hsiao ,  Yu-Te Lin ,  Yen-Hsi Li ,  Yung-Hsiang Chen ,  Jia-Min Shieh

IPC: G01N27/12 ,  G01N33/00 ,  G01N21/3504 ,  G01N27/62 ,  G01N21/359

Abstract: The present invention provides a miniature gas sensor, which comprises a gas sensor chip. The gas sensor chip includes a hollow structure on the back. An insulating layer is disposed below the sensing material. A miniature heating device is disposed surrounding the sensing material. The sensing material is adhered to the sensing electrodes. The sensing material includes two metal oxide semiconductors or a compound structure of the sensing layer having a metal oxide semiconductor and a reaction layer with a rough surface. An interface layer is sandwiched between the two metal oxide layers for increasing the efficiency in sensing gas. The gas sensor according to the present invention can be implemented on silicon substrate with hollow structures. In addition, the size of the chip can be miniaturized.

公开(公告)号：US10600915B2

公开(公告)日：2020-03-24

申请号：US15905729

申请日：2018-02-26

Applicant: National Applied Research Laboratories

Inventor： Wen-Hsien Huang ,  Jia-Min Shieh ,  Chang-Hong Shen

IPC: H01L29/786 ,  H01L21/324 ,  H01L21/02 ,  H01L29/66 ,  H01L23/538 ,  H01L23/498 ,  H01L29/423 ,  H01L27/12

Abstract: A flexible substrate structure including a flexible substrate, a first dielectric layer, a metal-containing layer and a second dielectric layer is provided. The first dielectric layer is located on the flexible substrate. The metal-containing layer has a reflectivity greater than 15% and a heat transfer coefficient greater than 2 W/m-K. The metal-containing layer is disposed between the first dielectric layer and the second dielectric layer, and the second dielectric layer is an inorganic material layer. A flexible transistor including the above-mentioned flexible substrate structure and a method for fabricating the same are also provided.

公开(公告)号：US10446694B2

公开(公告)日：2019-10-15

申请号：US15620846

申请日：2017-06-13

Applicant: National Applied Research Laboratories

Inventor： Kai-Shin Li ,  Bo-Wei Wu ,  Min-Cheng Chen ,  Jia-Min Shieh ,  Wen-Kuan Yeh

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/778 ,  H01L29/10

Abstract: A field-effect transistor structure having two-dimensional transition metal dichalcogenides includes a substrate, a source/drain structure, a two-dimensional (2D) channel layer, and a gate layer. The source/drain structure is disposed on the substrate and has a surface higher than a surface of the substrate. The 2D channel layer is disposed on the source and the drain and covers the space between the source and the drain. The gate layer is disposed between the source and the drain and covers the 2D channel layer. The field-effect transistor having two-dimensional transition metal dichalcogenides is a planar field-effect transistor or a fin field-effect transistor.

公开(公告)号：US09905547B2

公开(公告)日：2018-02-27

申请号：US14883227

申请日：2015-10-14

Applicant: National Applied Research Laboratories

Inventor： Chang-Hong Shen ,  Jia-Min Shieh ,  Wen-Hsien Huang ,  Tsung-Ta Wu ,  Chih-Chao Yang ,  Tung-Ying Hsieh

IPC: H01L31/062 ,  H01L25/16 ,  H01L23/58 ,  H01L31/028 ,  H01L31/075

CPC classification number: H01L25/167 ,  H01L23/58 ,  H01L31/028 ,  H01L31/075 ,  Y02E10/547 ,  Y02E10/548

Abstract: A chipset with light energy harvester, includes a substrate, a functional element layer, and a light energy harvesting layer, both are stacked vertically on the substrate, and an interconnects connected between the functional element layer and the light energy harvesting layer.

公开(公告)号：US20250133968A1

公开(公告)日：2025-04-24

申请号：US18921034

申请日：2024-10-21

Applicant: National Applied Research Laboratories

Inventor： Ya-Jui Tsou ,  Duan-Lee Tang ,  Yuan-Chen Sun ,  Kai-Shin Li ,  Ya-Ling Wu ,  Jia-Min Shieh

IPC: H10N50/10 ,  G11C11/16 ,  H10B61/00 ,  H10N50/80

Abstract: The present invention provides a spin-orbit torque magnetoresistive memory structure, which comprises a first conductive layer, a magnetic tunneling junction (MTJ) layer, a channel layer, and a second conductive layer stacked sequentially. The MTJ layer is disposed on the first conductive layer. The channel layer is disposed on the MTJ layer. The second conductive layer is disposed on the channel layer. These structures are fabricated sequentially using lithography. By forming the MTJ layer before the channel layer, redeposition of the metal of the channel layer on the MTJ layer can be avoided.

公开(公告)号：US20180358474A1

公开(公告)日：2018-12-13

申请号：US15620846

申请日：2017-06-13

Applicant: National Applied Research Laboratories

Inventor： Kai-Shin Li ,  Bo-Wei Wu ,  Min-Cheng Chen ,  Jia-Min Shieh ,  Wen-Kuan Yeh

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/02697 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/778 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618

Abstract: A field-effect transistor structure having two-dimensional transition metal dichalcogenides includes a substrate, a source/drain structure, a two-dimensional (2D) channel layer, and a gate layer. The source/drain structure is disposed on the substrate and has a surface higher than a surface of the substrate. The 2D channel layer is disposed on the source and the drain and covers the space between the source and the drain. The gate layer is disposed between the source and the drain and covers the 2D channel layer. The field-effect transistor having two-dimensional transition metal dichalcogenides is a planar field-effect transistor or a fin field-effect transistor.