-
公开(公告)号：US20050156257A1
公开(公告)日：2005-07-21
申请号：US11066762
申请日：2005-02-28
申请人： Nestor Bojarczuk , Kevin Chan , Christopher D'Emic , Evgeni Gousev , Supratik Guha , Paul Jamison , Lars-Ake Ragnarsson
发明人： Nestor Bojarczuk , Kevin Chan , Christopher D'Emic , Evgeni Gousev , Supratik Guha , Paul Jamison , Lars-Ake Ragnarsson
IPC分类号： H01L21/8238 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/513 , H01L21/28194
摘要： A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.
-
公开(公告)号：US20060289903A1
公开(公告)日：2006-12-28
申请号：US11513101
申请日：2006-08-30
申请人： Wanda Andreoni , Alessandro Callegari , Eduard Cartier , Alessandro Curioni , Christopher D'Emic , Evgeni Gousev , Michael Gribelyuk , Paul Jamison , Rajarao Jammy , Dianne Lacey , Fenton McFeely , Vijay Narayanan , Carlo Pignedoli , Joseph Shepard , Sufi Zafar
发明人： Wanda Andreoni , Alessandro Callegari , Eduard Cartier , Alessandro Curioni , Christopher D'Emic , Evgeni Gousev , Michael Gribelyuk , Paul Jamison , Rajarao Jammy , Dianne Lacey , Fenton McFeely , Vijay Narayanan , Carlo Pignedoli , Joseph Shepard , Sufi Zafar
IPC分类号： H01L31/112 , H01L29/80
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译： 本发明提供具有高移动性和低界面电荷的栅堆叠结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。 在本发明中使用的高温退火提供了一种栅堆叠结构，其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或 更少，约250cm 2 / Vs或更高的峰迁移率，并且在约6.0×10 12反转电荷/ cm 2处基本上没有迁移率降解， 或更大。
-
公开(公告)号：US20060202279A1
公开(公告)日：2006-09-14
申请号：US11413532
申请日：2006-04-29
CPC分类号： H01L21/28202 , H01L21/02247 , H01L21/02326 , H01L21/02337 , H01L21/0234 , H01L21/28255 , H01L21/3143 , H01L21/31658 , H01L21/318 , H01L29/518 , Y10S438/906 , Y10S438/933
摘要： A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.
-
公开(公告)号：US20050070122A1
公开(公告)日：2005-03-31
申请号：US10672631
申请日：2003-09-27
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L21/318 , H01L29/51 , H01L21/469
CPC分类号： H01L21/28202 , H01L21/02247 , H01L21/02326 , H01L21/02337 , H01L21/0234 , H01L21/28255 , H01L21/3143 , H01L21/31658 , H01L21/318 , H01L29/518 , Y10S438/906 , Y10S438/933
摘要： A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.
摘要翻译： 公开了用作栅极电介质的Ge基材料上产生6nm以下等效氧化物厚度薄的锗氮氧化物层的方法。 该方法涉及两步法。 首先，在Ge基材料的表层中加入氮。 其次，氮掺入之后是氧化步骤。 该方法为基于Ge的场效应器件（例如MOS晶体管）的高质量栅极电介质产生优异的厚度控制。 还公开了具有薄氮氧化锗栅电介质的器件的结构和用这种器件制造的处理器。
-
公开(公告)号：US20050087822A1
公开(公告)日：2005-04-28
申请号：US10982999
申请日：2004-11-05
申请人： Mukesh Khare , Christopher D'Emic , Thomas Hwang , Paul Jamison , James Quinlivan , Beth Ward
发明人： Mukesh Khare , Christopher D'Emic , Thomas Hwang , Paul Jamison , James Quinlivan , Beth Ward
IPC分类号： H01L21/265 , H01L21/28 , H01L21/314 , H01L21/318 , H01L29/51 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L21/31 , H01L21/469
CPC分类号： H01L29/518 , H01L21/28202 , H01L21/2822 , H01L21/3144
摘要： A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.
摘要翻译： 一种用于形成用于集成电路器件的栅极电介质的方法。 在本发明的示例性实施例中，该方法包括在基底材料上形成初始氧氮化物层，该氮氧化物层具有初始物理厚度。 然后对初始氧氮化物层进行等离子体氮化处理，等离子体氮化导致最终的氧氮化物层具有最终的物理厚度。
-
公开(公告)号：US20050280105A1
公开(公告)日：2005-12-22
申请号：US10873733
申请日：2004-06-22
申请人： Wanda Andreoni , Alessandro Callegari , Eduard Cartier , Alessandro Curioni , Christopher D'Emic , Evengi Gousev , Michael Gribelyuk , Paul Jamison , Rajarao Jammy , Dianne Lacey , Fenton McFeely , Vijay Narayanan , Carlo Pignedoli , Joseph Shepard , Sufi Zafar
发明人： Wanda Andreoni , Alessandro Callegari , Eduard Cartier , Alessandro Curioni , Christopher D'Emic , Evengi Gousev , Michael Gribelyuk , Paul Jamison , Rajarao Jammy , Dianne Lacey , Fenton McFeely , Vijay Narayanan , Carlo Pignedoli , Joseph Shepard , Sufi Zafar
IPC分类号： H01L21/00 , H01L21/28 , H01L21/336 , H01L21/84 , H01L29/49 , H01L29/51 , H01L29/76 , H01L29/78 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译： 本发明提供具有高移动性和低界面电荷的栅堆叠结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（约800℃）。 在本发明中使用的高温退火提供了一种栅堆叠结构，其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或 更少，约250cm 2 / Vs或更高的峰迁移率，并且在约6.0×10 12反转电荷/ cm 2处基本上不会迁移率降低， 或更大。
-
7.发明申请METHOD OF REPLACING SILICON WITH METAL IN INTEGRATED CIRCUIT CHIP FABRICATION 审中-公开在集成电路芯片制造中用金属替代硅的方法公开(公告)号：US20140015051A1
公开(公告)日：2014-01-16
申请号：US14031120
申请日：2013-09-19
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/76283 , H01L21/76879 , H01L21/76886 , H01L21/823437 , H01L21/823481 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66772
摘要： A method of replacing semiconductor material with metal, Replacement Metal Gate Field Effect Transistors (RMG FETs) and Contacts (RMCs), and Integrated Circuit (IC) chips including the FETs and/or RMCs. A patterned semiconductor layer, e.g., silicon, is formed on a dielectric layer, e.g., a layered gate dielectric. A field dielectric layer fills between shapes in the patterned semiconductor layer. Metal is deposited on the shapes. The wafer is annealed to replace semiconductor in each shape with metal to form metal FET gates or contacts.
摘要翻译： 用金属替代半导体材料的方法，替代金属栅场效应晶体管（RMG FET）和触点（RMC）以及包括FET和/或RMC的集成电路（IC）芯片。 图案化的半导体层，例如硅，形成在电介质层，例如层状栅极电介质上。 场介电层填充图案化的半导体层中的形状之间。 金属沉积在形状上。 将晶片退火以用金属代替每种形状的半导体，以形成金属FET栅极或触点。
-
8.发明授权公开(公告)号：US08580635B2
公开(公告)日：2013-11-12
申请号：US13310796
申请日：2011-12-05
IPC分类号： H01L21/8238
CPC分类号： H01L27/088 , H01L21/76283 , H01L21/76879 , H01L21/76886 , H01L21/823437 , H01L21/823481 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66772
摘要： A method of replacing semiconductor material with metal, Replacement Metal Gate Field Effect Transistors (RMG FETs) and Contacts (RMCs), and Integrated Circuit (IC) chips including the FETs and/or RMCs. A patterned semiconductor layer, e.g., silicon, is formed on a dielectric layer, e.g., a layered gate dielectric. A field dielectric layer fills between shapes in the patterned semiconductor layer. Metal is deposited on the shapes. The wafer is annealed to replace semiconductor in each shape with metal to form metal FET gates or contacts.
摘要翻译： 用金属替代半导体材料的方法，替代金属栅场效应晶体管（RMG FET）和触点（RMC）以及包括FET和/或RMC的集成电路（IC）芯片。 图案化的半导体层，例如硅，形成在电介质层，例如层状栅极电介质上。 场介电层填充图案化的半导体层中的形状之间。 金属沉积在形状上。 将晶片退火以用金属代替每种形状的半导体，以形成金属FET栅极或触点。
-
公开(公告)号：US08828138B2
公开(公告)日：2014-09-09
申请号：US12781514
申请日：2010-05-17
申请人： Stephen W. Bedell , Christopher D'Emic , Hongbo Peng , Sufi Zafar
发明人： Stephen W. Bedell , Christopher D'Emic , Hongbo Peng , Sufi Zafar
IPC分类号： C30B1/06 , G01N27/414 , B82Y15/00
CPC分类号： B82Y15/00 , G01N27/02 , G01N27/4145 , G01N33/48721
摘要： A method of using a sensor comprising a field effect transistor (FET) embedded in a nanopore includes placing the sensor in an electrolyte comprising at least one of biomolecules and deoxyribonucleic acid (DNA); placing an electrode in the electrolyte; applying a gate voltage in the sub-threshold regime to the electrode; applying a drain voltage to a drain of the FET; applying a source voltage to a source of the FET; detecting a change in a drain current in the sensor in response to the at least one of biomolecules and DNA passing through the nanopore.
摘要翻译： 使用包含嵌入在纳米孔中的场效应晶体管（FET）的传感器的方法包括将传感器放置在包含生物分子和脱氧核糖核酸（DNA）中的至少一种的电解质中; 将电极放置在电解质中; 将所述子阈值状态中的栅极电压施加到所述电极; 将漏极电压施加到FET的漏极; 将源电压施加到FET的源极; 响应于生物分子和通过纳米孔的DNA中的至少一个，检测传感器中的漏极电流的变化。
-
10.发明申请METHOD OF REPLACING SILICON WITH METAL IN INTEGRATED CIRCUIT CHIP FABRICATION 有权在集成电路芯片制造中用金属替代硅的方法公开(公告)号：US20130140634A1
公开(公告)日：2013-06-06
申请号：US13310796
申请日：2011-12-05
IPC分类号： H01L29/786 , H01L21/283 , H01L21/28
CPC分类号： H01L27/088 , H01L21/76283 , H01L21/76879 , H01L21/76886 , H01L21/823437 , H01L21/823481 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66772
摘要： A method of replacing semiconductor material with metal, Replacement Metal Gate Field Effect Transistors (RMG FETs) and Contacts (RMCs), and Integrated Circuit (IC) chips including the FETs and/or RMCs. A patterned semiconductor layer, e.g., silicon, is formed on a dielectric layer, e.g., a layered gate dielectric. A field dielectric layer fills between shapes in the patterned semiconductor layer. Metal is deposited on the shapes. The wafer is annealed to replace semiconductor in each shape with metal to form metal FET gates or contacts.
摘要翻译： 用金属替代半导体材料的方法，替代金属栅场效应晶体管（RMG FET）和触点（RMC）以及包括FET和/或RMC的集成电路（IC）芯片。 图案化的半导体层，例如硅，形成在电介质层，例如层状栅极电介质上。 场介电层填充图案化的半导体层中的形状之间。 金属沉积在形状上。 将晶片退火以用金属代替每种形状的半导体，以形成金属FET栅极或触点。
-
-
-
-
-
-
-
-
-
搜索结果
10 条记录 (耗时 0.025 秒)