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    FORMATION OF HIGH-K GATE STACKS IN SEMICONDUCTOR DEVICES
    6.
    发明申请
    FORMATION OF HIGH-K GATE STACKS IN SEMICONDUCTOR DEVICES 有权
    在半导体器件中形成高K栅极堆叠

    公开(公告)号：US20100171187A1

    公开(公告)日：2010-07-08

    申请号：US12637787

    申请日：2009-12-15

    申请人： Wanda Andreoni ,  Alessandro Curioni ,  Carlo A. Pignedoli

    发明人： Wanda Andreoni ,  Alessandro Curioni ,  Carlo A. Pignedoli

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

    摘要： A method of forming a high-K gate stack for a MOSFET device to control the threshold voltage for the MOSFET device. A first high-K metallic oxide layer is formed on a semiconductor substrate. At least one composite layer is then formed directly on the first layer. The composite layer is composed of a second high-K metallic oxide layer formed directly on a dipole induction layer. The dipole induction layer includes a high-K metallic oxide having higher oxygen vacancy affinity and lower oxygen vacancy diffusivity than the first and second layers. A metallic gate electrode is then formed on the composite layer. Formation of the various layers is such as to position the dipole induction layer of the composite layer between the gate electrode and substrate so as to shift the threshold voltage to a desired level. A high-K gate stack in a MOSFET device formed by the above method is also provided.

    摘要翻译： 形成用于MOSFET器件的高K栅极堆叠以控制MOSFET器件的阈值电压的方法。 第一高K金属氧化物层形成在半导体衬底上。 然后在第一层上直接形成至少一个复合层。 复合层由直接形成在偶极感应层上的第二高K金属氧化物层组成。 偶极子诱导层包括具有比第一和第二层更高的氧空位亲和力和更低的氧空位扩散率的高K金属氧化物。 然后在复合层上形成金属栅电极。 各层的形成使得将复合层的偶极子感应层定位在栅电极和衬底之间，以将阈值电压移动到期望的水平。 还提供了通过上述方法形成的MOSFET器件中的高K栅极堆叠。

    Formation of high-K gate stacks in semiconductor devices
    7.
    发明授权
    Formation of high-K gate stacks in semiconductor devices 有权
    在半导体器件中形成高K栅极叠层

    公开(公告)号：US08273618B2

    公开(公告)日：2012-09-25

    申请号：US12637787

    申请日：2009-12-15

    申请人： Wanda Andreoni ,  Alessandro Curioni ,  Carlo A. Pignedoli

    发明人： Wanda Andreoni ,  Alessandro Curioni ,  Carlo A. Pignedoli

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

    摘要： A method of forming a high-K gate stack for a MOSFET device to control the threshold voltage for the MOSFET device. A first high-K metallic oxide layer is formed on a semiconductor substrate. At least one composite layer is then formed directly on the first layer. The composite layer is composed of a second high-K metallic oxide layer formed directly on a dipole induction layer. The dipole induction layer includes a high-K metallic oxide having higher oxygen vacancy affinity and lower oxygen vacancy diffusivity than the first and second layers. A metallic gate electrode is then formed on the composite layer. Formation of the various layers is such as to position the dipole induction layer of the composite layer between the gate electrode and substrate so as to shift the threshold voltage to a desired level. A high-K gate stack in a MOSFET device formed by the above method is also provided.

    摘要翻译： 形成用于MOSFET器件的高K栅极堆叠以控制MOSFET器件的阈值电压的方法。 第一高K金属氧化物层形成在半导体衬底上。 然后在第一层上直接形成至少一个复合层。 复合层由直接形成在偶极感应层上的第二高K金属氧化物层组成。 偶极子诱导层包括具有比第一和第二层更高的氧空位亲和力和更低的氧空位扩散率的高K金属氧化物。 然后在复合层上形成金属栅电极。 各层的形成使得将复合层的偶极子感应层定位在栅电极和衬底之间，以将阈值电压移动到期望的水平。 还提供了通过上述方法形成的MOSFET器件中的高K栅极堆叠。

    Dielectric materials
    9.
    发明授权
    Dielectric materials 失效
    介电材料

    公开(公告)号：US07057244B2

    公开(公告)日：2006-06-06

    申请号：US10624021

    申请日：2003-07-21

    申请人： Wanda Andreoni ,  Alessandro Curioni ,  Stephen A. Shevlin

    发明人： Wanda Andreoni ,  Alessandro Curioni ,  Stephen A. Shevlin

    IPC分类号： H01L29/76

    CPC分类号： H01L21/02197 ,  C23C14/08 ,  C30B23/02 ,  C30B29/22 ,  H01L21/02269 ,  H01L21/28167 ,  H01L21/31604 ,  H01L21/31616 ,  H01L29/517

    摘要： An article of manufacture comprises a substrate and a layer of N(x)Y(1−x)AlO3 on the substrate where x is a molar fraction greater than zero and less than one, and N is an element selected from La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. The article may be an electronic device further comprising an electrode electrically isolated from the substrate by the layer. In particular, the dielectric properties of the layer are such that the layer is especially although by no means exclusively useful for electrically isolating gate electrodes in field effect transistor devices. The layer may be formed on the substrate via molecular beam epitaxy.

    摘要翻译： 一种制品包括在基底上的基底和一层N（x）Y（1-x）3 Al 3/3，其中x是 大于零且小于1的摩尔分数，N是选自La，Ce，Pr，Nd，Pm，Sm，Eu，Gd，Tb，Dy，Ho，Er，Tm，Yb和Lu中的元素。 物品可以是还包括通过该层与衬底电隔离的电极的电子器件。 特别地，该层的介电特性使得该层特别是尽管绝对不能用于场效应晶体管器件中的电绝缘栅电极。 层可以通过分子束外延形成在衬底上。