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    Formation of DRAM capacitor among metal interconnect
    1.
    发明授权
    Formation of DRAM capacitor among metal interconnect 有权
    在金属互连中形成DRAM电容

    公开(公告)号：US09565766B2

    公开(公告)日：2017-02-07

    申请号：US13976085

    申请日：2011-10-07

    申请人： Nick Lindert ,  Joseph M. Steigerwald ,  Kanwal Jit Singh

    发明人： Nick Lindert ,  Joseph M. Steigerwald ,  Kanwal Jit Singh

    IPC分类号： H05K1/18 ,  H01L27/108 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

    CPC分类号： H01L28/75 ,  H01L23/5223 ,  H01L23/53238 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/55 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91 ,  H01L2924/0002 ,  H05K1/182 ,  H01L2924/00

    摘要： Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.

    摘要翻译： 公开了用于在用于嵌入式DRAM应用的金属互连之间集成电容器的技术。 在一些实施例中，该技术使用湿蚀刻来完全去除在电容器形成之前暴露的互连金属（例如铜）。 这种互连金属去除排除了金属不会污染电容器的hi-k电介质。 另一个优点是电容器的高度（表面积）增加，这样可以增加电荷存储。 在一个示例实施例中，提供集成电路器件，其包括具有至少部分DRAM位单元电路的衬底，衬底上的互连层，并且包括一个或多个含金属的互连特征，以及至少部分地 在互连层中并且占据从其中去除含金属互连特征的空间。 集成电路设备可以是例如处理器或通信设备。

    FORMATION OF DRAM CAPACITOR AMONG METAL INTERCONNECT
    2.
    发明申请
    FORMATION OF DRAM CAPACITOR AMONG METAL INTERCONNECT 有权
    金属互连中DRAM电容器的形成

    公开(公告)号：US20130271938A1

    公开(公告)日：2013-10-17

    申请号：US13976085

    申请日：2011-10-07

    申请人： Nick Lindert ,  Joseph M. Steigerwald ,  Kanwal Jit Singh

    发明人： Nick Lindert ,  Joseph M. Steigerwald ,  Kanwal Jit Singh

    IPC分类号： H05K1/18

    CPC分类号： H01L28/75 ,  H01L23/5223 ,  H01L23/53238 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/55 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91 ,  H01L2924/0002 ,  H05K1/182 ,  H01L2924/00

    摘要： Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.

    摘要翻译： 公开了用于在用于嵌入式DRAM应用的金属互连之间集成电容器的技术。 在一些实施例中，该技术使用湿蚀刻来完全去除在电容器形成之前暴露的互连金属（例如铜）。 这种互连金属去除排除了金属不会污染电容器的hi-k电介质。 另一个优点是电容器的高度（表面积）增加，这样可以增加电荷存储。 在一个示例实施例中，提供集成电路器件，其包括具有至少部分DRAM位单元电路的衬底，衬底上的互连层，并且包括一个或多个含金属的互连特征，以及至少部分地 在互连层中并且占据从其中去除含金属互连特征的空间。 集成电路装置可以是例如处理器或通信装置。

    FULLY ENCAPSULATED CONDUCTIVE LINES
    3.
    发明申请
    FULLY ENCAPSULATED CONDUCTIVE LINES 审中-公开
    完全插入的导线

    公开(公告)号：US20130292797A1

    公开(公告)日：2013-11-07

    申请号：US13977542

    申请日：2011-12-21

    申请人： Nick Lindert ,  Kanwal Jit Singh ,  Byung-Chan Lee

    发明人： Nick Lindert ,  Kanwal Jit Singh ,  Byung-Chan Lee

    IPC分类号： H01L27/06 ,  H01L21/768

    CPC分类号： H01L27/0611 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/5223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Fully encapsulated conductive lines are generally described. For example, a first dielectric layer is formed on a substrate. Copper wiring is disposed below a top surface of the first dielectric layer. A barrier metal layer is formed over the copper wiring, the barrier metal layer flush with the top surface of the first dielectric layer, and a second dielectric layer is formed on the barrier metal layer and the top surface of the first dielectric layer. Other embodiments are also disclosed and claimed.

    摘要翻译： 通常描述完全封装的导电线。 例如，在基板上形成第一电介质层。 铜布线设置在第一介电层的顶表面下方。 在铜布线上形成阻挡金属层，阻挡金属层与第一电介质层的顶表面齐平，并且在阻挡金属层和第一介电层的顶表面上形成第二电介质层。 还公开并要求保护其他实施例。

    SELF-ALIGNED VIA PATTERNING WITH MULTI-COLORED PHOTOBUCKETS FOR BACK END OF LINE (BEOL) INTERCONNECTS
    5.
    发明申请
    SELF-ALIGNED VIA PATTERNING WITH MULTI-COLORED PHOTOBUCKETS FOR BACK END OF LINE (BEOL) INTERCONNECTS 审中-公开
    自动对准通过多行彩色胶片的背面（BEOL）互连

    公开(公告)号：US20150255284A1

    公开(公告)日：2015-09-10

    申请号：US14720821

    申请日：2015-05-24

    申请人： Robert L. Bristol ,  James M. Blackwell ,  Alan M. Myers ,  Kanwal Jit Singh

    发明人： Robert L. Bristol ,  James M. Blackwell ,  Alan M. Myers ,  Kanwal Jit Singh

    IPC分类号： H01L21/033 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

    CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer including a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure, the second layer including a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. First and second dielectric regions are disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The first dielectric region is composed of a first cross-linked photolyzable material, and the second dielectric region is composed of a second, different, cross-linked photolyzable material.

    摘要翻译： 描述了通过用于后端（BEOL）互连的多色photobuckets图案化的自对准。 在一个示例中，用于集成电路的互连结构包括布置在衬底上方的互连结构的第一层，第一层包括在第一方向上交替的金属线和介质线的第一光栅。 介质线具有高于金属线的最上表面的最上表面。 所述互连结构的第二层设置在所述互连结构的所述第一层上方，所述第二层包括垂直于所述第一方向的第二方向的交替金属线和介质线的第二光栅。 介质线具有比第二光栅的金属线的最下表面低的最低表面。 第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。 第一和第二电介质区域设置在第一光栅的金属线和第二光栅的金属线之间，并且在与第一光栅的介电线的上部和第二栅的介电线的下部相同的平面中 光栅。 第一电介质区域由第一交联光可光化材料组成，第二电介质区域由第二不同的交联光可光化材料组成。

    TECHNIQUES FOR FORMING INTERCONNECTS IN POROUS DIELECTRIC MATERIALS
    6.
    发明申请
    TECHNIQUES FOR FORMING INTERCONNECTS IN POROUS DIELECTRIC MATERIALS 有权
    在多孔电介质材料中形成互连的技术

    公开(公告)号：US20150179578A1

    公开(公告)日：2015-06-25

    申请号：US14139970

    申请日：2013-12-24

    申请人： Christopher J. Jezewski ,  David J. Michalak ,  Kanwal Jit Singh ,  Alan M. Myers

    发明人： Christopher J. Jezewski ,  David J. Michalak ,  Kanwal Jit Singh ,  Alan M. Myers

    IPC分类号： H01L23/532 ,  H01L21/768

    CPC分类号： H01L23/5329 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76838 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (κ-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer. Some embodiments can be utilized, for example, in processes involving atomic layer deposition (ALD)-based and/or chemical vapor deposition (CVD)-based backend metallization of highly porous, ultra-low-κ (ULK) dielectric materials.

    摘要翻译： 公开了用于在多孔电介质材料中形成互连的技术。 根据一些实施例，可以通过用诸如氮化钛（TiN），二氧化钛（TiO 2）或其它合适的牺牲材料的牺牲孔填充材料填充其孔来临时减小主介质层的孔隙率， 与互连的金属化和介电材料相比，具有高蚀刻选择性。 在填充电介质层内形成互连之后，可以从主电介质的孔中去除牺牲孔填充材料。 在一些情况下，可以对介电常数（＆kgr--value），泄漏性能和/或时间依赖的介电击穿（TDDB）性能的最小或其他可忽略的影响进行去除和固化。 一些实施例可以用于例如涉及基于原子层沉积（ALD）的和/或化学气相沉积（CVD）的后端金属化的高度多孔，超低kgr的金属化过程。 （ULK）电介质材料。

    Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects
    7.
    发明授权
    Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects 有权
    自对准通孔和插头图案化，用于后端（BEOL）互连的光触点

    公开(公告)号：US09236342B2

    公开(公告)日：2016-01-12

    申请号：US14133385

    申请日：2013-12-18

    申请人： Robert L. Bristol ,  Kevin Lin ,  Kanwal Jit Singh ,  Alan M. Myers ,  Richard E. Schenker

    发明人： Robert L. Bristol ,  Kevin Lin ,  Kanwal Jit Singh ,  Alan M. Myers ,  Richard E. Schenker

    IPC分类号： H01L21/311 ,  H01L23/522 ,  H01L21/768 ,  H01L21/027 ,  H01L23/532

    CPC分类号： H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76825 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The integrated circuit also includes a region of dielectric material disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material is composed of a cross-linked photolyzable material.

    摘要翻译： 描述了用于后端（BEOL）互连的带有光触点的自对准通孔和插头图案。 在一个示例中，用于集成电路的互连结构包括设置在衬底上方的互连结构的第一层，第一层具有在第一方向上交替的金属线和介质线的第一光栅。 介质线具有高于金属线的最上表面的最上表面。 集成电路还包括布置在互连结构的第一层之上的互连结构的第二层。 第二层包括垂直于第一方向的第二方向的交替金属线和介质线的第二光栅。 介质线具有比第二光栅的金属线的最下表面低的最低表面。 第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。 集成电路还包括设置在第一光栅的金属线和第二光栅的金属线之间的电介质材料区域，并且在与第一光栅的介质线的上部和电介质的下部相同的平面中 第二光栅的线。 介电材料的区域由交联的可光致发光材料组成。

    Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects
    10.
    发明授权
    Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects 有权
    对角线硬掩模，用于在制造后端线（BEOL）互连中改进覆盖层

    公开(公告)号：US09209077B2

    公开(公告)日：2015-12-08

    申请号：US14137588

    申请日：2013-12-20

    申请人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

    发明人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

    IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

    CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.

    摘要翻译： 描述了使用对角线硬掩模进行自对准通孔和插头图案，以改进制造后端（BEOL）互连的覆盖。 在一个示例中，制造用于集成电路的互连结构的方法包括在布置在衬底上方的层间介电层上形成第一硬掩模层。 第一硬掩模层包括多个第一硬掩模线，其具有在第一方向上的第一光栅，并且包括与第一光栅交错的一个或多个牺牲材料。 该方法还涉及在第一硬掩模层之上形成第二硬掩模层。 第二硬掩模层包括多个第二硬掩模线，所述第二硬掩模线在第二方向上具有与第一方向对角的第二光栅。 该方法还涉及使用第二硬掩模层作为掩模，蚀刻第一硬掩模层以形成图案化的第一硬掩模层。 蚀刻涉及去除一个或多个牺牲材料的一部分。