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    FULLY ENCAPSULATED CONDUCTIVE LINES
    1.
    发明申请
    FULLY ENCAPSULATED CONDUCTIVE LINES 审中-公开
    完全插入的导线

    公开(公告)号：US20130292797A1

    公开(公告)日：2013-11-07

    申请号：US13977542

    申请日：2011-12-21

    申请人： Nick Lindert ,  Kanwal Jit Singh ,  Byung-Chan Lee

    发明人： Nick Lindert ,  Kanwal Jit Singh ,  Byung-Chan Lee

    IPC分类号： H01L27/06 ,  H01L21/768

    CPC分类号： H01L27/0611 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/5223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Fully encapsulated conductive lines are generally described. For example, a first dielectric layer is formed on a substrate. Copper wiring is disposed below a top surface of the first dielectric layer. A barrier metal layer is formed over the copper wiring, the barrier metal layer flush with the top surface of the first dielectric layer, and a second dielectric layer is formed on the barrier metal layer and the top surface of the first dielectric layer. Other embodiments are also disclosed and claimed.

    摘要翻译： 通常描述完全封装的导电线。 例如，在基板上形成第一电介质层。 铜布线设置在第一介电层的顶表面下方。 在铜布线上形成阻挡金属层，阻挡金属层与第一电介质层的顶表面齐平，并且在阻挡金属层和第一介电层的顶表面上形成第二电介质层。 还公开并要求保护其他实施例。

    Formation of DRAM capacitor among metal interconnect
    2.
    发明授权
    Formation of DRAM capacitor among metal interconnect 有权
    在金属互连中形成DRAM电容

    公开(公告)号：US09565766B2

    公开(公告)日：2017-02-07

    申请号：US13976085

    申请日：2011-10-07

    申请人： Nick Lindert ,  Joseph M. Steigerwald ,  Kanwal Jit Singh

    发明人： Nick Lindert ,  Joseph M. Steigerwald ,  Kanwal Jit Singh

    IPC分类号： H05K1/18 ,  H01L27/108 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

    CPC分类号： H01L28/75 ,  H01L23/5223 ,  H01L23/53238 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/55 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91 ,  H01L2924/0002 ,  H05K1/182 ,  H01L2924/00

    摘要： Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.

    摘要翻译： 公开了用于在用于嵌入式DRAM应用的金属互连之间集成电容器的技术。 在一些实施例中，该技术使用湿蚀刻来完全去除在电容器形成之前暴露的互连金属（例如铜）。 这种互连金属去除排除了金属不会污染电容器的hi-k电介质。 另一个优点是电容器的高度（表面积）增加，这样可以增加电荷存储。 在一个示例实施例中，提供集成电路器件，其包括具有至少部分DRAM位单元电路的衬底，衬底上的互连层，并且包括一个或多个含金属的互连特征，以及至少部分地 在互连层中并且占据从其中去除含金属互连特征的空间。 集成电路设备可以是例如处理器或通信设备。

    FORMATION OF DRAM CAPACITOR AMONG METAL INTERCONNECT
    3.
    发明申请
    FORMATION OF DRAM CAPACITOR AMONG METAL INTERCONNECT 有权
    金属互连中DRAM电容器的形成

    公开(公告)号：US20130271938A1

    公开(公告)日：2013-10-17

    申请号：US13976085

    申请日：2011-10-07

    申请人： Nick Lindert ,  Joseph M. Steigerwald ,  Kanwal Jit Singh

    发明人： Nick Lindert ,  Joseph M. Steigerwald ,  Kanwal Jit Singh

    IPC分类号： H05K1/18

    CPC分类号： H01L28/75 ,  H01L23/5223 ,  H01L23/53238 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/55 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91 ,  H01L2924/0002 ,  H05K1/182 ,  H01L2924/00

    摘要： Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.

    摘要翻译： 公开了用于在用于嵌入式DRAM应用的金属互连之间集成电容器的技术。 在一些实施例中，该技术使用湿蚀刻来完全去除在电容器形成之前暴露的互连金属（例如铜）。 这种互连金属去除排除了金属不会污染电容器的hi-k电介质。 另一个优点是电容器的高度（表面积）增加，这样可以增加电荷存储。 在一个示例实施例中，提供集成电路器件，其包括具有至少部分DRAM位单元电路的衬底，衬底上的互连层，并且包括一个或多个含金属的互连特征，以及至少部分地 在互连层中并且占据从其中去除含金属互连特征的空间。 集成电路装置可以是例如处理器或通信装置。

    Penetrating implant for forming a semiconductor device
    4.
    发明授权
    Penetrating implant for forming a semiconductor device 有权
    用于形成半导体器件的穿透植入物

    公开(公告)号：US08426927B2

    公开(公告)日：2013-04-23

    申请号：US13107783

    申请日：2011-05-13

    申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    IPC分类号： H01L29/66 ,  H01L21/02

    CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

    摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

    摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

    Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performance
    7.
    发明申请
    Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performance 审中-公开
    制造具有用于改变窄宽度器件性能的抗卤素的MOSFET晶体管的方法

    公开(公告)号：US20070145495A1

    公开(公告)日：2007-06-28

    申请号：US11319815

    申请日：2005-12-27

    申请人： Giuseppe Curello ,  Sivakumar Mudanai ,  Nick Lindert ,  Leonard Pipes ,  M. Shaheed ,  Sunit Tyagi

    发明人： Giuseppe Curello ,  Sivakumar Mudanai ,  Nick Lindert ,  Leonard Pipes ,  M. Shaheed ,  Sunit Tyagi

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/823481 ,  H01L21/823412

    摘要： A method including forming a transistor structure structure comprising a gate electrode over an active region of a substrate, the active region defined by a trench isolation structure and changing a performance of a narrow width transistor with respect to a wide width transistor by introducing a dopant into the active region adjacent an interface defined by the trench isolation structure and the gate electrode. A structure including a gate electrode formed on a substrate, an active region adjacent an interface defined by a trench isolation structure and a gate electrode and an implant within the active region to change a performance of a transistor.

    摘要翻译： 一种包括在衬底的有源区上形成包括栅电极的晶体管结构结构的方法，所述有源区由沟槽隔离结构限定，并且通过将掺杂剂引入到宽宽度晶体管中来改变窄宽晶体管的性能 邻接由沟槽隔离结构和栅电极限定的界面的有源区。 一种结构，包括形成在衬底上的栅电极，与由沟槽隔离结构限定的界面相邻的有源区和栅电极以及有源区内的注入以改变晶体管的性能。

    Controlled faceting of source/drain regions
    9.
    发明授权
    Controlled faceting of source/drain regions 有权
    源极/漏极区域的受控面

    公开(公告)号：US06946350B2

    公开(公告)日：2005-09-20

    申请号：US10750158

    申请日：2003-12-31

    申请人： Nick Lindert ,  Justin K. Brask

    发明人： Nick Lindert ,  Justin K. Brask

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/045 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7848

    摘要： Numerous embodiments of a method for highly selective faceting of the S/D regions in a CMOS device are described. In one embodiment, source/drain regions are formed on a substrate. The source/drain regions are wet etched to form faceted regions. A silicon germanium layer is formed on the faceted regions of the source/drain regions to yield a strained device.

    摘要翻译： 描述了用于CMOS器件中的S / D区域的高选择性刻面的方法的许多实施例。 在一个实施例中，源极/漏极区域形成在衬底上。 源极/漏极区域被湿蚀刻以形成刻面区域。 在源极/漏极区的多面区域上形成硅锗层以产生应变器件。

    Epitaxially deposited source/drain
    10.
    发明申请
    Epitaxially deposited source/drain 有权
    外延沉积源/漏极

    公开(公告)号：US20050087801A1

    公开(公告)日：2005-04-28

    申请号：US10692696

    申请日：2003-10-24

    申请人： Nick Lindert ,  Anand Murthy ,  Justin Brask

    发明人： Nick Lindert ,  Anand Murthy ,  Justin Brask

    IPC分类号： H01L21/336 ,  H01L31/119

    CPC分类号： H01L29/66628 ,  H01L29/66636

    摘要： An epitaxially deposited source/drain extension may be formed for a metal oxide semiconductor field effect transistor. A sacrificial layer may be formed and etched away to undercut under the gate electrode. Then a source/drain extension of epitaxial silicon may be deposited to extend under the edges of the gate electrode. As a result, the extent by which the source/drain extension extends under the gate may be controlled by controlling the etching of the sacrificial material. Its thickness and depth may be controlled by controlling the deposition process. Moreover, the characteristics of the source/drain extension may be controlled independently of those of the subsequently formed deep or heavily doped source/drain junction.

    摘要翻译： 可以为金属氧化物半导体场效应晶体管形成外延沉积的源极/漏极延伸。 可以形成牺牲层并蚀刻掉在栅电极下方的底切。 然后，可以沉积外延硅的源极/漏极延伸部，以在栅电极的边缘下延伸。 结果，可以通过控制牺牲材料的蚀刻来控制源极/漏极延伸在栅极下延伸的程度。 其厚度和深度可以通过控制沉积过程来控制。 此外，可以独立于后续形成的深度或重掺杂源极/漏极结的特性来控制源极/漏极延伸的特性。