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公开(公告)号：US11650817B2
公开(公告)日：2023-05-16
申请号：US17276598
申请日：2019-09-18
Applicant: Optimum Semiconductor Technologies Inc.
Inventor： Mayan Moudgill , Murugappan Senthilvelan
IPC: G06F9/30
CPC classification number: G06F9/30036 , G06F9/3013 , G06F9/30018
Abstract: A processor includes a register file comprising a length register, a vector register file comprising a plurality of vector registers, a mask register file comprising a plurality of mask registers, and a vector instruction execution circuit to execute a masked vector instruction comprising a first length register identifier representing the length register, a first vector register identifier representing a first vector register of the vector register file, and a first mask register identifier representing a first mask register of the mask register file, wherein the length register is to store a length value representing a number of operations to be applied to data elements stored in the first vector register, the first mask register is to store a plurality of mask bits, and a first mask bit of the plurality of mask bits determines whether a corresponding first one of the operations causes an effect.
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公开(公告)号：US10733140B2
公开(公告)日：2020-08-04
申请号：US14727051
申请日：2015-06-01
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Arthur Joseph Hoane , Paul Hurtley
Abstract: A computer processor is disclosed. The computer processor may comprises a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more instructions that produce results with elements of widths different than that of the input elements. The computer processor may be implemented as a monolithic integrated circuit.
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公开(公告)号：US10719451B2
公开(公告)日：2020-07-21
申请号：US15868513
申请日：2018-01-11
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , A. Joseph Hoane , Lei Wang , Gary Nacer , Aaron G. Milbury , Enrique A. Barria , Paul Hurtley
IPC: G06F12/1027 , G06F12/1036 , G06F12/1009 , G06F12/0864
Abstract: A processor includes a translation lookaside buffer (TLB) comprising a plurality of ways, wherein each way is associated with a respective page size, and a processing core, communicatively coupled to the TLB, to execute an instruction associated with a virtual memory page, identify a first way of the plurality of ways, wherein the first way is associated with a first page size, determine an index value using the virtual memory page and the first page size for the first way, determine, using the index value, a first TLB entry of the first way, and translate, using a memory address translation stored in the first TLB entry, the first virtual memory page to a first physical memory page.
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4.发明申请公开(公告)号：US20160314074A1
公开(公告)日：2016-10-27
申请号：US15087150
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
CPC classification number: G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F2212/452 , G06F2212/60 , G06F2212/602
Abstract: A computer processor that implements pre-translation of virtual addresses is disclosed. The computer processor may include a register file comprising one or more registers. The computer processor may include processing logic. The processing logic may receive a value to store in a register of one or more registers. The processing logic may store the value in the register. The processing logic may designate the received value as a virtual address, the virtual address having a corresponding virtual base page number. The processing logic may translate the virtual base page number to a corresponding real base page number and zero or more real page numbers corresponding to zero or more virtual page numbers adjacent to the virtual base page number. The processing logic may further store in the register of the one or more registers the real base page number and the zero or more real page numbers.
Abstract translation: 公开了实现虚拟地址的预翻译的计算机处理器。 计算机处理器可以包括包括一个或多个寄存器的寄存器文件。 计算机处理器可以包括处理逻辑。 处理逻辑可以接收一个值以存储在一个或多个寄存器的寄存器中。 处理逻辑可以将该值存储在寄存器中。 处理逻辑可以将接收的值指定为虚拟地址，虚拟地址具有对应的虚拟基页号。 处理逻辑可以将虚拟基页编号转换为对应的真实基页编号和对应于与虚拟基页编号相邻的零个或多个虚拟页码的零个或多个实际页号。 处理逻辑还可以在一个或多个寄存器的寄存器中存储真实的基页号码和零个或多个实际页码。
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5.发明申请VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING ONE OR MORE COMPLEX ARITHMETIC INSTRUCTIONS 审中-公开使用一个或多个复杂算术指令配置在可变长度向量上运行的矢量处理器公开(公告)号：US20160224340A1
公开(公告)日：2016-08-04
申请号：US14724061
申请日：2015-05-28
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Sitij Agrawal
IPC: G06F9/30
CPC classification number: G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F9/461 , G06F9/462 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more complex arithmetic instructions. The computer processor may be implemented as a monolithic integrated circuit.
Abstract translation: 公开了一种计算机处理器。 计算机处理器可以包括向量单元，其包括向量寄存器文件，其包括至少一个寄存器以保存不同数量的元件。 计算机处理器还可以包括处理逻辑，其被配置为使用一个或多个复数运算指令对矢量寄存器堆中的变化数量的元件进行操作。 计算机处理器可以被实现为单片集成电路。
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Patent Agency Ranking
公开(公告)号：US12165030B2
公开(公告)日：2024-12-10
申请号：US17351434
申请日：2021-06-18
Applicant: Optimum Semiconductor Technologies Inc.
Inventor： Mayan Moudgill , John Glossner
Abstract: A system and method include an accelerator circuit comprising an input circuit block, a filter circuit block, a post-processing circuit block, and an output circuit block and a processor to initialize the accelerator circuit, determining tasks of a neural network application to be performed by at least one of the input circuit block, the filter circuit block, the post-processing circuit block, or the output circuit block, assign each of the tasks to a corresponding one of the input circuit block, the filter circuit block, the post-processing circuit block, or the output circuit block, instruct the accelerator circuit to perform the tasks, and execute the neural network application based on results received from the accelerator circuit completing performance of the tasks.
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公开(公告)号：US20180173625A1
公开(公告)日：2018-06-21
申请号：US15841974
申请日：2017-12-14
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , A. Joseph Hoane
IPC: G06F12/0817 , G06F9/52 , G06F9/30 , G06F9/54 , G06F12/0811
Abstract: A processor comprising a cache, the cache comprising a cache line, an execution unit to execute an atomic primitive to responsive to executing a read instruction to retrieve a data item from a memory location, cause to store a copy of the data item in the cache line, execute a lock instruction to lock the cache line to the processor, execute at least one instruction while the cache line is locked to the processor, and execute an unlock instruction to cause the cache controller to release the cache line from the processor.
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8.发明授权公开(公告)号：US09940129B2
公开(公告)日：2018-04-10
申请号：US15087269
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC: G06F12/08 , G06F9/30 , G06F3/06 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F12/0862 , G06F9/32 , G06F9/355
CPC classification number: G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F2212/452 , G06F2212/60 , G06F2212/602
Abstract: A computer processor with register direct branches and employing an instruction preload structure is disclosed. The computer processor may include a hierarchy of memories comprising a first memory organized in a structure having one or more entries for one or more addresses corresponding to one or more instructions. The one or more entries of the one or more addresses may have a starting address. The structure may have one or more locations for storing the one or more instructions. The computer processor may include one or more registers to which one or more corresponding instruction addresses are writable. The computer processor may include processing logic. In response to the processing logic writing the one or more instruction addresses to the one or more registers, the processing logic may to pre-fetch the one or more instructions of a linear sequence of instructions from a first memory level of the hierarchy of memories into a second memory level of the hierarchy of memories beginning at the starting address. At least one address of the one or more addresses may be the contents of a register of the one or more registers.
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公开(公告)号：US09910824B2
公开(公告)日：2018-03-06
申请号：US14727076
申请日：2015-06-01
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
CPC classification number: G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more instructions that separate a vector or combine two vectors. The computer processor may be implemented as a monolithic integrated circuit.
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公开(公告)号：US11157407B2
公开(公告)日：2021-10-26
申请号：US15841974
申请日：2017-12-14
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , A. Joseph Hoane
IPC: G06F12/0817 , G06F9/30 , G06F12/084 , G06F12/0895 , G06F9/52 , G06F9/54 , G06F12/0811
Abstract: A processor comprising a cache, the cache comprising a cache line, an execution unit to execute an atomic primitive to responsive to executing a read instruction to retrieve a data item from a memory location, cause to store a copy of the data item in the cache line, execute a lock instruction to lock the cache line to the processor, execute at least one instruction while the cache line is locked to the processor, and execute an unlock instruction to cause the cache controller to release the cache line from the processor.
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