中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

27 records (took 0.015 seconds)

    System and method to implement masked vector instructions
    3.
    发明授权
    System and method to implement masked vector instructions 有权

    公开(公告)号：US11650817B2

    公开(公告)日：2023-05-16

    申请号：US17276598

    申请日：2019-09-18

    Applicant: Optimum Semiconductor Technologies Inc.

    Inventor： Mayan Moudgill ,  Murugappan Senthilvelan

    IPC: G06F9/30

    CPC classification number: G06F9/30036 ,  G06F9/3013 ,  G06F9/30018

    Abstract: A processor includes a register file comprising a length register, a vector register file comprising a plurality of vector registers, a mask register file comprising a plurality of mask registers, and a vector instruction execution circuit to execute a masked vector instruction comprising a first length register identifier representing the length register, a first vector register identifier representing a first vector register of the vector register file, and a first mask register identifier representing a first mask register of the mask register file, wherein the length register is to store a length value representing a number of operations to be applied to data elements stored in the first vector register, the first mask register is to store a plurality of mask bits, and a first mask bit of the plurality of mask bits determines whether a corresponding first one of the operations causes an effect.

    IMPLEMENTATION OF REGISTER RENAMING, CALL-RETURN PREDICTION AND PREFETCH
    6.
    发明申请
    IMPLEMENTATION OF REGISTER RENAMING, CALL-RETURN PREDICTION AND PREFETCH 审中-公开

    公开(公告)号：US20180203703A1

    公开(公告)日：2018-07-19

    申请号：US15868497

    申请日：2018-01-11

    Applicant: Optimum Semiconductor Technologies, Inc.

    Inventor： Mayan Moudgill ,  Gary Nacer ,  A. Joseph Hoane ,  Paul Hurtley ,  Murugappan Senthilvelan

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A processor includes a plurality of physical registers and a processor core, communicatively coupled to the plurality of physical registers, the processor core to execute a process comprising a plurality of instructions to responsive to issuance of a call instruction for out-of-order execution, identify, based on a head pointer of the plurality of physical registers, a first physical register of the plurality of physical registers, store a return address in the first physical register, wherein the first physical register is associated with a first identifier, store, based on an out-of-order pointer of a call stack associated with the process, the first identifier in a first entry of the call stack, and increment, modulated by a length of the call stack, the out-of-order pointer of the call stack to point to a second entry of the call stack.

    COMPUTER PROCESSOR WITH REGISTER DIRECT BRANCHES AND EMPLOYING AN INSTRUCTION PRELOAD STRUCTURE
    7.
    发明申请
    COMPUTER PROCESSOR WITH REGISTER DIRECT BRANCHES AND EMPLOYING AN INSTRUCTION PRELOAD STRUCTURE 有权
    具有注册直接分支机构的计算机处理器，并采用指令性预告结构

    公开(公告)号：US20160314071A1

    公开(公告)日：2016-10-27

    申请号：US15087269

    申请日：2016-03-31

    Applicant: Optimum Semiconductor Technologies, Inc.

    Inventor： Mayan Moudgill ,  Gary Nacer ,  C. John Glossner ,  A. Joseph Hoane ,  Paul Hurtley ,  Murugappan Senthilvelan ,  Pablo Balzola

    IPC: G06F12/08 ,  G06F12/10

    CPC classification number: G06F9/30029 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0673 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/3013 ,  G06F9/322 ,  G06F9/355 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1009 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602

    Abstract: A computer processor with register direct branches and employing an instruction preload structure is disclosed. The computer processor may include a hierarchy of memories comprising a first memory organized in a structure having one or more entries for one or more addresses corresponding to one or more instructions. The one or more entries of the one or more addresses may have a starting address. The structure may have one or more locations for storing the one or more instructions. The computer processor may include one or more registers to which one or more corresponding instruction addresses are writable. The computer processor may include processing logic. In response to the processing logic writing the one or more instruction addresses to the one or more registers, the processing logic may to pre-fetch the one or more instructions of a linear sequence of instructions from a first memory level of the hierarchy of memories into a second memory level of the hierarchy of memories beginning at the starting address. At least one address of the one or more addresses may be the contents of a register of the one or more registers.

    Abstract translation: 公开了一种具有寄存器直接分支和采用指令预加载结构的计算机处理器。 计算机处理器可以包括存储器层级，其包括以具有一个或多个对应于一个或多个指令的地址的一个或多个地址的一个或多个条目的结构组织的第一存储器。 一个或多个地址的一个或多个条目可以具有起始地址。 该结构可以具有用于存储一个或多个指令的一个或多个位置。 计算机处理器可以包括一个或多个寄存器，一个或多个对应的指令地址可写入到该寄存器。 计算机处理器可以包括处理逻辑。 响应于将一个或多个指令地址写入一个或多个寄存器的处理逻辑，处理逻辑可以从存储器层级的第一存储器级别预先获取线性指令序列的一个或多个指令， 从起始地址开始的存储器层级的第二存储器级别。 一个或多个地址的至少一个地址可以是一个或多个寄存器的寄存器的内容。

    PROCESSOR WITH ADVANCED OPERATING SYSTEM SUPPORT
    10.
    发明申请
    PROCESSOR WITH ADVANCED OPERATING SYSTEM SUPPORT 审中-公开
    具有高级操作系统支持的处理器

    公开(公告)号：US20160364236A1

    公开(公告)日：2016-12-15

    申请号：US15155570

    申请日：2016-05-16

    Applicant: Optimum Semiconductor Technologies, Inc.

    Inventor： Mayan Moudgill ,  Gary Nacer ,  C. John Glossner ,  Arthur Joseph Hoane ,  Paul Hurtley ,  Murugappan Senthilvelan

    IPC: G06F9/30

    CPC classification number: G06F9/30189 ,  G06F9/3005 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/462

    Abstract: A computer processor may include a plurality of hardware threads. The computer processor may further include state processor logic for a state of a hardware thread. The state processor logic may include per thread logic that contains state that is replicated in each hardware thread of the plurality of hardware threads and common logic that is independent of each hardware thread of the plurality of hardware threads. The computer processor may further include single threaded mode logic to execute instructions in a single threaded mode from only one hardware thread of the plurality of hardware threads. The computer processor may further include second mode logic to execute instructions in a second mode from more than one hardware thread of the plurality of hardware threads simultaneously. The computer processor may further include witching mode logic to switch between the first mode and the second mode.

    Abstract translation: 计算机处理器可以包括多个硬件线程。 计算机处理器还可以包括用于硬件线程的状态的状态处理器逻辑。 状态处理器逻辑可以包括每个线程逻辑，其包含在多个硬件线程的每个硬件线程中被复制的状态和独立于多个硬件线程中的每个硬件线程的公共逻辑。 计算机处理器还可以包括单线程模式逻辑，以仅从多个硬件线程中的一个硬件线程以单线程模式执行指令。 计算机处理器还可以包括第二模式逻辑，用于同时执行来自多个硬件线程的多于一个硬件线程的第二模式的指令。 计算机处理器还可以包括在第一模式和第二模式之间切换的巫师模式逻辑。

Patent Agency Ranking