公开(公告)号：US20100055869A1

公开(公告)日：2010-03-04

申请号：US12588087

申请日：2009-10-02

申请人： Osamu Arisumi ,  Masahiro Kiyotoshi ,  Katsuhiko Hieda ,  Yoshitaka Tsunashima

发明人： Osamu Arisumi ,  Masahiro Kiyotoshi ,  Katsuhiko Hieda ,  Yoshitaka Tsunashima

IPC分类号： H01L21/762

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底中形成沟槽，在沟槽中形成具有第一凹陷部分的第一绝缘膜，形成涂膜以便将其涂覆在第一凹部中，将涂膜转变为 第二绝缘膜，平坦化第二绝缘膜以暴露第一绝缘膜和第二绝缘膜，至少从第一凹部去除第二绝缘膜，以调节形成在沟槽中的第一凹部的纵横比，由此形成 在其中形成第二凹部，在半导体衬底的表面上形成第三绝缘膜，以便填充第二凹部。

公开(公告)号：US07618876B2

公开(公告)日：2009-11-17

申请号：US11227252

申请日：2005-09-16

申请人： Osamu Arisumi ,  Masahiro Kiyotoshi ,  Katsuhiko Hieda ,  Yoshitaka Tsunashima

发明人： Osamu Arisumi ,  Masahiro Kiyotoshi ,  Katsuhiko Hieda ,  Yoshitaka Tsunashima

IPC分类号： H01L21/76 ,  H01L21/44

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底中形成沟槽，在沟槽中形成具有第一凹陷部分的第一绝缘膜，形成涂膜以便将其涂覆在第一凹部中，将涂膜转变为 第二绝缘膜，平坦化第二绝缘膜以暴露第一绝缘膜和第二绝缘膜，至少从第一凹部去除第二绝缘膜，以调节形成在沟槽中的第一凹部的纵横比，由此形成 在其中形成第二凹部，在半导体衬底的表面上形成第三绝缘膜，以便填充第二凹部。

公开(公告)号：US20060270170A1

公开(公告)日：2006-11-30

申请号：US11227252

申请日：2005-09-16

申请人： Osamu Arisumi ,  Masahiro Kiyotoshi ,  Katsuhiko Hieda ,  Yoshitaka Tsunashima

发明人： Osamu Arisumi ,  Masahiro Kiyotoshi ,  Katsuhiko Hieda ,  Yoshitaka Tsunashima

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底中形成沟槽，在沟槽中形成具有第一凹陷部分的第一绝缘膜，形成涂膜以便将其涂覆在第一凹部中，将涂膜转变为 第二绝缘膜，平坦化第二绝缘膜以暴露第一绝缘膜和第二绝缘膜，至少从第一凹部去除第二绝缘膜，以调节形成在沟槽中的第一凹部的纵横比，由此形成 在其中形成第二凹部，在半导体衬底的表面上形成第三绝缘膜，以便填充第二凹部。

公开(公告)号：US06278164B1

公开(公告)日：2001-08-21

申请号：US08996704

申请日：1997-12-23

申请人： Katsuhiko Hieda ,  Yoshitaka Tsunashima ,  Keitaro Imai ,  Tomonori Aoyama

发明人： Katsuhiko Hieda ,  Yoshitaka Tsunashima ,  Keitaro Imai ,  Tomonori Aoyama

IPC分类号： H01L2976

CPC分类号： H01L29/513 ,  H01L29/4983 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/78391

摘要： A p-type silicon substrate has an element isolation region of an STI structure formed therein. A transistor region isolated by the isolation region has a n-type source/drain diffusion layer. Further, a p-channel impurity layer is formed substantially only in its channel region for controlling its threshold voltage (Vth). A gate insulator film consisting of a high dielectric film is formed on the channel region with an Si3N4 film interposed therebetween. A metal gate electrode having its bottom and side surfaces covered with the gate insulator film is provided in a self-alignment manner with respect to the source/drain diffusion layer.

摘要翻译： p型硅衬底具有形成在其中的STI结构的元件隔离区域。 由隔离区隔离的晶体管区域具有n型源极/漏极扩散层。 此外，p沟道杂质层基本上仅在其沟道区域中形成，用于控制其阈值电压（Vth）。 在沟道区域上形成由高介电膜构成的栅极绝缘膜，其间插入有Si 3 N 4膜。 相对于源极/漏极扩散层以自对准的方式设置具有被栅极绝缘膜覆盖的底部和侧面的金属栅电极。

公开(公告)号：US07772076B2

公开(公告)日：2010-08-10

申请号：US11715965

申请日：2007-03-09

申请人： Atsushi Yagishita ,  Kouji Matsuo ,  Yasushi Akasaka ,  Kyoichi Suguro ,  Yoshitaka Tsunashima

发明人： Atsushi Yagishita ,  Kouji Matsuo ,  Yasushi Akasaka ,  Kyoichi Suguro ,  Yoshitaka Tsunashima

IPC分类号： H01L21/336

CPC分类号： H01L29/66575 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/1033 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/78 ,  Y10S438/926

摘要： A method of manufacturing a semiconductor device includes forming a dummy gate wiring layer having a side surface and an upper surface on a first area of one major surface of a substrate, the major surface of the substrate including the first area and a second area, thereafter, forming a semiconductor film on the second area of the major surface of the substrate by using epitaxial growth, the semiconductor film having a thickness smaller than a thickness of the dummy gate wiring layer, and forming, on the semiconductor film, a gate sidewall which is made of an insulator and covers the side surface of the dummy gate wiring layer.

摘要翻译： 一种制造半导体器件的方法包括在衬底的一个主表面的第一区域上形成具有侧表面和上表面的虚拟栅极布线层，所述衬底的主表面包括第一区域和第二区域，之后 通过使用外延生长在所述衬底的主表面的第二区域上形成半导体膜，所述半导体膜的厚度小于所述虚拟栅极布线层的厚度，并且在所述半导体膜上形成栅极侧壁，所述栅极侧壁 由绝缘体制成并覆盖虚拟栅极布线层的侧表面。

公开(公告)号：US20090233451A1

公开(公告)日：2009-09-17

申请号：US12471830

申请日：2009-05-26

申请人： Yoshitaka Tsunashima ,  Seiji Ihumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

发明人： Yoshitaka Tsunashima ,  Seiji Ihumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

IPC分类号： H01L21/31

CPC分类号： H01L21/82345 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31604 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656

摘要： Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.

摘要翻译： 权利要求和公开的是一种半导体器件，包括具有在包含金属，硅和氧的金属硅酸盐的化合物中含有氮或氟的栅极绝缘膜结构的晶体管，具有非晶态金属氧化物层叠结构的栅极绝缘膜结构 膜和金属硅酸盐膜，或具有包括第一金属元素的氧化物膜的第一栅极绝缘膜和包括第二金属元素的金属硅酸盐膜的第二栅极绝缘膜的栅极绝缘膜结构。

公开(公告)号：US20080224252A1

公开(公告)日：2008-09-18

申请号：US12068635

申请日：2008-02-08

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L29/00

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

摘要翻译： 在使用外延生长方法选择性地在硅衬底上生长其上要形成元素的外延层时，形成外延层，以便在作为元件隔离绝缘膜的热氧化膜上方向上延伸， 以防止形成小平面。 随后，通过CMP去除外延层的不需要的部分以完成STI元件隔离结构。

公开(公告)号：US07372113B2

公开(公告)日：2008-05-13

申请号：US10880508

申请日：2004-07-01

申请人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

发明人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

IPC分类号： H01L21/314

CPC分类号： H01L21/022 ,  H01L21/0217 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/76838 ,  H01L21/76897 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/792

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，栅电极，形成在半导体衬底和栅电极之间的第一绝缘膜，以及沿着栅电极的顶表面或侧表面形成的第二绝缘膜， 包含氮，硅和氢的氮化硅膜和形成在下部氮化硅膜上并含有氮，硅和氢的上部氮化硅膜，并且其中氮（N）与硅（Si）的组成比N / Si在 下氮化硅膜比上述氮化硅膜高。

公开(公告)号：US07208797B2

公开(公告)日：2007-04-24

申请号：US10023849

申请日：2001-12-21

申请人： Atsushi Yagishita ,  Kouji Matsuo ,  Yasushi Akasaka ,  Kyoichi Suguro ,  Yoshitaka Tsunashima

发明人： Atsushi Yagishita ,  Kouji Matsuo ,  Yasushi Akasaka ,  Kyoichi Suguro ,  Yoshitaka Tsunashima

IPC分类号： H01L29/94 ,  H01L29/76

CPC分类号： H01L29/66575 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/1033 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/78 ,  Y10S438/926

摘要： There is provided a semiconductor device including a substrate, a device isolation insulating film formed on the substrate, a gate electrode formed on the substrate, a gate wiring layer formed in the device isolation insulating film and connected to the gate electrode, source and drain electrodes arranged on the substrate to face each other via the gate electrode, and an insulating film covering bottom and side surfaces of each of the gate electrode and the gate wiring layer, wherein the gate, source and drain electrodes and gate wiring layer have upper surface levels equal to or lower than that of the device isolation insulating film.

摘要翻译： 提供了一种半导体器件，包括衬底，在衬底上形成的器件隔离绝缘膜，形成在衬底上的栅电极，形成在器件隔离绝缘膜中并连接到栅电极的栅极布线层，源极和漏极 布置在基板上，经由栅极电极相对对置;以及绝缘膜，其覆盖栅极电极和栅极布线层中的每一个的底部和侧面，其中栅极，源极和漏极以及栅极布线层具有上表面水平 等于或低于器件绝缘膜的绝缘膜。

公开(公告)号：US06989316B2

公开(公告)日：2006-01-24

申请号：US10406281

申请日：2003-04-04

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L21/20

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.