公开(公告)号：US11782852B2

公开(公告)日：2023-10-10

申请号：US17208354

申请日：2021-03-22

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Tadashi Ono ,  Isao Kato ,  Yoshihisa Inagaki ,  Shuichi Ohki

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/4282 ,  G06F2213/0026

Abstract: When a part of a signal line of a first interface and a part of a signal line of a second interface share a signal line and there is a memory connected to both the interfaces, initialization of the second interface and initialization of the memory are executed in parallel following initialization of the first interface.

公开(公告)号：US12117887B2

公开(公告)日：2024-10-15

申请号：US18122977

申请日：2023-03-17

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tadashi Ono ,  Yoshihisa Inagaki

IPC: G06F1/32 ,  G06F1/04 ,  G06F1/3296

CPC classification number: G06F1/3296 ,  G06F1/04

Abstract: When a host-slave system including a host device and a slave device transitions to a power-down mode, the host device drives a CMD line in order of a high level, a low level, and a high level, and stops supplying a clock signal after a predetermined time elapses. During a power-down mode period, the slave device stops supplying a power to a back-end module. When the host device resumes the supply of the clock signal, the host-slave system returns from the power-down mode.

公开(公告)号：US12026007B2

公开(公告)日：2024-07-02

申请号：US17729520

申请日：2022-04-26

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tadashi Ono ,  Isao Kato

IPC: G06F1/10 ,  G06F1/08 ,  G06F9/4401

CPC classification number: G06F1/10 ,  G06F1/08 ,  G06F9/4416

Abstract: A data transfer system includes a slave device, and a host device that is connected to the slave device via at least a power supply line, a clock line, a command line, and a data line. A CMD line is continuously driven to a low level in a period from when the supply of at least a first clock is stopped to when the second clock is supplied (period form timing t5 to timing t6).

公开(公告)号：US20240393854A1

公开(公告)日：2024-11-28

申请号：US18795811

申请日：2024-08-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tadashi Ono

IPC: G06F1/26

Abstract: The host device supplies power with a first voltage to the slave device through the first power supply line, instructs the slave device through the signal line to check compatibility with a power input with a second voltage lower than the first voltage, and instructs the slave device on voltage switch through the signal line when the slave device is compatible with the power input with the second voltage. When receiving a normal response from the slave device to the instruction for the voltage switch, the host device supplies the power with the second voltage to the slave device through the second power supply line, and stops supplying the power with the first voltage to the slave device through the first power supply line.

公开(公告)号：US10339083B2

公开(公告)日：2019-07-02

申请号：US15397999

申请日：2017-01-04

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tadashi Ono ,  Tatsuya Adachi

IPC: G06F13/364 ,  G06F13/42

Abstract: In a removable system formed from a host device and a slave device detachable from the host device, when the slave device sequentially detects a signal of a first voltage level and a signal of a second voltage level from the connected host device, the signal of the first voltage level is transmitted by a second signal line. Subsequently, when the host device detects that the second signal line is at the first voltage level, the host device interrupts drive of a first signal line, and executes initialization.

公开(公告)号：US11880225B2

公开(公告)日：2024-01-23

申请号：US17841054

申请日：2022-06-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tadashi Ono ,  Isao Kato ,  Takuji Maeda

IPC: G06F1/06 ,  G06F9/4401 ,  G06F1/3215

CPC classification number: G06F9/4403 ,  G06F1/06 ,  G06F1/3215

Abstract: A slave device continuously transmits a plurality of tuning blocks to a host device at intervals defined by a clock period between a plurality of data blocks at the time of transmitting the plurality of data blocks and by a clock period defined by a data structure of the plurality of tuning blocks.

公开(公告)号：US11055499B2

公开(公告)日：2021-07-06

申请号：US16738919

申请日：2020-01-09

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Yoshihisa Inagaki ,  Tadashi Ono ,  Isao Kato

IPC: G06K19/06 ,  G06K7/00

Abstract: A card device according to an aspect of the present disclosure includes: a first interface that connects the card device with a host device. The card device notifies, through the first interface, the host device of whether or not the card device includes a second interface different from the first interface.

公开(公告)号：US10055356B2

公开(公告)日：2018-08-21

申请号：US15451884

申请日：2017-03-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tadashi Ono

IPC: G06F12/1027 ,  G06F3/06 ,  G06F12/128

CPC classification number: G06F12/1027 ,  G06F3/0607 ,  G06F3/0616 ,  G06F3/0643 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/128 ,  G06F2212/68 ,  G06F2212/70 ,  G06F2212/7203

Abstract: Provided is a memory device with improved memory region usage efficiency. The memory device includes flash memory including: a control information (FAT) region that stores FAT for a file and a user data (UD) region that stores UD; cache memory including a FAT cache region that stores all or part of the FAT; an I/F that receives a write command for writing one of the FAT and the UD; and a memory controller that determines whether write data to be written is the FAT or the UD based on an address included in the write command, and sets the size of the FAT cache region based on an update frequency or an update count for the address included in the write command for the write data determined to be the FAT by the determiner.