Abstract:
A circuit assembly which includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. A first element having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on one of its surfaces is mounted on and at least partially supported at its second surface by the first surface of the semiconductor die. The first element is positioned such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected at its first end to either the semiconductor die electrical contact or the first element electrical contact. A method of manufacturing this circuit assembly is also disclosed.
Abstract:
An electronic system circuit package is disclosed herein. The package utilizes a lead frame having an electrically conductive component support segment incorporating provisions for mounting a plurality of electronic components directly on the support segment in accordance with a predetermined circuit design. The circuit package is then encapsulated in a dielectric medium. In a preferred embodiment, at least some of the electronic components are mounted directly to electrically isolated subsegments of the component support segment and electrically interconnected through their respective subsegments to other components.
Abstract:
A circuit assembly which includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. A first element having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on one of its surfaces is mounted on and at least partially supported at its second surface by the first surface of the semiconductor die. The first element is positioned such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected at its first end to either the semiconductor die electrical contact or the first element electrical contact. A method of manufacturing this circuit assembly is also disclosed.
Abstract:
A lead frame for use in an integrated circuit package is disclosed herein. The lead frame includes a magnetic component winding wherein the winding is formed as an integral part of the lead frame. Additional windings may be formed as an integral part of the lead frame and then folded into position over the first winding to form a multiple layered magnetic component winding. In one embodiment, the lead frame based winding is coated with a magnetic material to form a lead frame based inductor. There is also disclosed a method of producing a lead frame including a magnetic component winding wherein the winding is formed as an integral part of the lead frame.
Abstract:
The invention provides a method and apparatus for picking a separated semiconductor die 128 from a wafer and placing it on a die attach pad 144 for bonding thereto. In a preferred embodiment, the apparatus comprises a die collet having a body 124 with a proximal end 123 and a distal end 125; at least one pair of spaced-apart walls 136 extending distally from the distal end of the body and having opposing faces 181 defining an aperture 126, the faces of the walls being sloped such that a distal portion of the aperture is wider than the die and a proximal portion of the aperture is narrower than the die; a recess 152 on the faces of the walls extending substantially the length of the die, the recess having a distally-facing surface 154 for contacting at least a portion of the top side 138 of the die; and means for holding the die in the aperture, usually including a vacuum port 128. The method comprises providing a collet like the aforementioned; positioning the aperture 126 over a die 120; exerting a vacuum pressure through the vacuum port 128 to retain the die in the aperture such that a portion of the top side contacts the distally-facing surface 154 of the recess 152; positioning the die over the pad 144 such that the bottom side of the die is parallel to the pad; and discontinuing the vacuum pressure to release the die from the aperture.
Abstract:
In semiconductor packing, a method and device for reducing thermal stress on a die and for reinforcing the strength of a die, A thermally-conductive member is positioned in a cooperating manner with the die during the packaging process.
Abstract:
In semiconductor packaging, a method and device for reducing thermal stress on a die and for reinforcing the strength of a die. A thermally-conductive member is positioned in a cooperating manner with the die during the packaging process.
Abstract:
A circuit assembly which includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. A first element having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on one of its surfaces is mounted on and at least partially supported at its second surface by the first surface of the semiconductor die. The first element is positioned such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected at its first end to either the semiconductor die electrical contact or the first element electrical contact. A method of manufacturing this circuit assembly is also disclosed.
Abstract:
An electric packaging arrangement for isolated circuits is described. A lead frame is formed with at least one off-centered tie bar connected between one of the circuits on the lead frame's internal lead and an external handling side rail. The tie bar is off-centered by a specified distance from the longitudinal center line of the package. The external side rail is used to support and align the lead frame during manufacturing. To meet safety requirements, such as the UL-1950 requirements, electrical components in a primary circuit and a secondary circuit are attached and electrically coupled to the lead frame in a manner such that the smallest internal distance between internal circuits is at least a predefined distance. The external distance between the tie bar, connected to the secondary circuit, and the closest primary circuit pin is set to meet external circuit component spacing requirements for isolated circuits. The described arrangement has a number of applications including packaging isolated circuits using small form factor packages such as dual-in-line (DIP) and small outline (SO) packages.
Abstract:
The invention provides a method and apparatus for picking a separated semiconductor die 128 from a wafer and placing it on a die attach pad 144 for bonding thereto. In a preferred embodiment, the apparatus comprises a die collet having a body 124 with a proximal end 123 and a distal end 125; at least one pair of spaced-apart walls 136 extending distally from the distal end of the body and having opposing faces 181 defining an aperture 126, the faces of the walls being sloped such that a distal portion of the aperture is wider than the die and a proximal portion of the aperture is narrower than the die; a recess 152 on the faces of the walls extending substantially the length of the die, the recess having a distally-facing surface 154 for contacting at least a portion of the top side 138 of the die; and means for holding the die in the aperture, usually including a vacuum port 128. The method comprises providing a collet like the aforementioned; positioning the aperture 126 over a die 120; exerting a vacuum pressure through the vacuum port 128 to retain the die in the aperture such that a portion of the top side contacts the distally-facing surface 154 of the recess 152; positioning the die over the pad 144 such that the bottom side of the die is parallel to the pad; and discontinuing the vacuum pressure to release the die from the aperture.