公开(公告)号：US20180047687A1

公开(公告)日：2018-02-15

申请号：US15233902

申请日：2016-08-10

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Jie FU ,  Manuel ALDRETE ,  Jonghae KIM ,  Changhan Hobie YUN ,  David Francis BERDY ,  Chengjie ZUO ,  Mario Francisco VELEZ

IPC: H01L23/00 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/09 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15321 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device according to some examples of the disclosure may include a package substrate, a semiconductor die coupled to one side of the package substrate with a first set of contacts on an active side of the semiconductor die and coupled to a plurality of solder prints with a second set of contacts on a back side of the semiconductor die. The semiconductor die may include a plurality of vias connecting the first set of contacts to the second set of contacts and configured to allow heat to be transferred from the active side of the die to the plurality of solder prints for a shorter heat dissipation path.

公开(公告)号：US20190067141A1

公开(公告)日：2019-02-28

申请号：US15691696

申请日：2017-08-30

Applicant: QUALCOMM Incorporated

Inventor： Jie FU ,  Hong Bok WE ,  Manuel ALDRETE

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/027 ,  H01L21/683

Abstract: Conventional packages for 5G applications suffer from disadvantages including high mold stress on the die, reduced performance, and increased keep-out zone. To address these and other issues of the conventional packages, it is proposed to pre-apply a wafer-applied material, which remains in place, to form an air cavity between the die and the substrate. The air cavity can enhance the die's performance. Also, since the wafer-applied material can remain in place, the keep-out zone can be reduced. As a result, higher density modules can be fabricated.

公开(公告)号：US20180228016A1

公开(公告)日：2018-08-09

申请号：US15429144

申请日：2017-02-09

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Jie FU ,  Manuel ALDRETE ,  Babak NEJATI ,  Husnu Ahmet MASARACIOGLU

IPC: H05K1/02 ,  H05K3/30 ,  H05K1/11 ,  H05K13/00 ,  H05K3/40

CPC classification number: H05K1/023 ,  H01L23/552 ,  H01L24/49 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/0216 ,  H05K1/115 ,  H05K3/30 ,  H05K3/4038 ,  H05K9/0024 ,  H05K13/00 ,  H05K2201/0715 ,  H01L2224/45099

Abstract: In a package such as a radio frequency (RF) module, an external shield may be provided to shield the package from external influences as well as to shield the devices within the package from undesirable affecting devices outside of the package. The package may also include an internal shield to suppress adverse effects of the signal generated by an aggressor device within the external shield to other devices within the external shield.

公开(公告)号：US20170084523A1

公开(公告)日：2017-03-23

申请号：US14861619

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Jie FU ,  Daeik Daniel KIM ,  Manuel ALDRETE ,  Chin-Kwan KIM ,  David BERDY ,  Niranjan Sunil MUDAKATTE ,  Changhan YUN ,  Je-Hsiung LAN ,  Jonghae KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/49805 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/3025 ,  H01R12/79 ,  H01L2224/81

Abstract: Conventional ways of coupling die packages to external devices include providing contacts on a separate area on a printed circuit board (PCB). These PCB contacts are configured to mate with connector contacts of a connector to enable coupling with external devices. Unfortunately, the PCB contacts take up significant amount of area of the PCB. Also, the connection can suffer from parasitic losses and signal integrity can be compromised. An on-package connection is proposed to address the short comings of the conventional ways. The on-package connection enables a die package to connect directly with the connector. This removes the need to provide a separate area for PCB contacts. Also, parasitic losses are minimized and signal integrity is enhanced.

公开(公告)号：US20160247754A1

公开(公告)日：2016-08-25

申请号：US14859318

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jie FU ,  Chin-Kwan KIM ,  Manuel ALDRETE ,  Milind Pravin SHAH ,  Dwayne Richard SHIRLEY

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: An integrated circuit package includes a substrate/interposer assembly having a plurality of conductive contacts and a plurality of conductive posts, such as copper posts, electrically coupled to at least some of the conductive contacts in the substrate/interposer assembly. The conductive posts are surrounded by a protective dielectric, such as a photoimageable dielectric (PID). An integrated circuit die may be disposed on the substrate/interposer assembly within an interior space surrounded by the dielectric. An additional integrated circuit die may be provided in a package-on-package (POP) configuration.

Abstract translation: 集成电路封装包括具有多个导电触点和多个导电柱（例如铜柱）的基板/插入件组件，其电耦合到衬底/插入器组件中的至少一些导电触点。 导电柱被诸如可光成像电介质（PID）的保护电介质包围。 集成电路管芯可以设置在由电介质包围的内部空间内的衬底/插入件组件上。 可以在封装封装（POP）配置中提供附加的集成电路管芯。

公开(公告)号：US20180316319A1

公开(公告)日：2018-11-01

申请号：US15584000

申请日：2017-05-01

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Shu ZHANG ,  Bonhoon KOO ,  Manuel ALDRETE ,  Jie FU ,  Chin-Kwan KIM ,  Babak NEJATI ,  Husnu Ahmet MASARACIOGLU

IPC: H03F1/52 ,  H03F3/189 ,  H03F3/20 ,  H03F1/56 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L23/12

CPC classification number: H01L23/12 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/645 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2224/16237 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/49175

Abstract: In exemplary aspects of the disclosure, magnetic coupling problems in a power amplifier/antenna circuit may be address by using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate to offer full RF isolation of both PA output match inductors (self-shielded and embedded) or using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate along with a component level conformal shield around the self-shielded inductor on the assembly structure.