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    Operation of field-effect transistor circuits having substantial distributed capacitance
    1.
    发明授权
    Operation of field-effect transistor circuits having substantial distributed capacitance 失效
    具有主要分布电容的场效应晶体管电路的运行

    公开(公告)号：US3688264A

    公开(公告)日：1972-08-29

    申请号：US3688264D

    申请日：1971-04-22

    Applicant: RCA CORP

    Inventor： DINGWALL ANDREW G F

    IPC: G11C11/412 ,  G11C11/419 ,  H03K3/353 ,  H03K17/041 ,  G11C11/40 ,  G11C5/02

    CPC classification number: H03K3/353 ,  G11C11/412 ,  G11C11/419 ,  H03K17/04106

    Abstract: The distributed capacitance at circuit node between conduction paths of interconnected field-effect transistors of a memory array is maintained charged to a fixed value during the major portion of the memory operating time. As one example, the distributed capacitance at the columns of an integrated circuit of a memory chip may be connected to the charging source except for the times during which any location on that chip is being accessed. Operation in this way opens sneak paths in the circuit and reduces power dissipation.

    Abstract translation: 在存储器操作时间的主要部分期间，存储器阵列的互连场效应晶体管的传导路径之间的电路节点处的分布电容被保持充电到固定值。 作为一个示例，除了正在访问该芯片上的任何位置的时间之外，存储器芯片的集成电路的列处的分布电容可以连接到充电源。 以这种方式操作可以打开电路中的潜行路径，并降低功耗。

    Ratio-compensated resistors for integrated circuit
    5.
    发明授权
    Ratio-compensated resistors for integrated circuit 失效
    用于集成电路的比例补偿电阻

    公开(公告)号：US3644802A

    公开(公告)日：1972-02-22

    申请号：US3644802D

    申请日：1968-05-31

    Applicant: RCA CORP

    Inventor： DINGWALL ANDREW G F

    IPC: H01L27/08 ,  H01L11/00

    CPC classification number: H01L27/0802 ,  Y10S257/925

    Abstract: The ratio of the resistances of two diffused integrated circuit resistors of dissimilar geometries is made relatively insensitive to processing variations in the structure of the resistors in different devices. Wider resistors in a given device are made more sensitive to width variations to match the greater sensitivity of narrower resistors in that device, and longer resistors are made more sensitive to length variations to match the greater sensitivity of shorter resistors. Lower value resistors are made less sensitive to metallurgical phenomena that affect contact resistance so that proportionally less contact resistance change is produced by a given processing variation in the lower value resistors than in the higher value resistors.

    Method of fabrication of photomasks
    7.
    发明授权
    Method of fabrication of photomasks 失效
    光电子制造方法

    公开(公告)号：US3673018A

    公开(公告)日：1972-06-27

    申请号：US3673018D

    申请日：1969-05-08

    Applicant: RCA CORP

    Inventor： DINGWALL ANDREW G F

    IPC: G03B27/58 ,  G03F1/00 ,  H01L21/00 ,  H01L21/027 ,  C23F1/02

    CPC classification number: H01L21/00 ,  G03F1/50 ,  G03F1/58

    Abstract: A PHOTOMASK HAS MULTILAYER OPAQUE PLATTERNS ON A TRANSPARENT SUBSTRATE. EACH PATTERN INCLUDES A BOTTOM LAYER AND A TOP LAYER, EACH OF A MATERIAL CAPABLE OF BEING ETCHED BY A SUBSTANCE WHICH WILL NOT ETCH THE SUBSTRATE, AND AN INTERMEDIATE LAYER OF A MATERIAL CAPABLE OF BEING ETCHED BY A SUBSTANCE WHICH WILL NOT ETCH THE BOTTOM AND TOP LAYERS. THE SEVERAL LAYERS COMPENSATE FOR DEFECTS IN EACH LAYER. AN IMPROVED PHOTOMASK FABRICATION METHOD INCLUDES FORMING THE ABOVEMENTIONED PATTERNS BY SUCCESSIVELY DEPOSITING THE BOTTOM AND INTERMEDIATE LAYERS, PHOTOETCHING THE INTERMEDIATE LAYER INTO A DESIRED PATTERN, DEPOSITING THE TOP LAYER, AND THEN PHOTOETCHING THE TOP AND BOTTOM LAYERS INTO A DESIRED PATTERN.

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