公开(公告)号：US20180261467A1

公开(公告)日：2018-09-13

申请号：US15760905

申请日：2015-10-01

Applicant: Renesas Electronics Corporation

Inventor： Masahiro MATSUMOTO ,  Kazuhito ICHINOSE ,  Akira YAJIMA

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00

Abstract: It is possible to prevent deterioration of a redistribution layer due to exposure of the redistribution layer from an upper insulating film and the resultant reaction with moisture, ions, or the like. As means thereof, in a semiconductor device having a plurality of wiring layers formed in an element formation region and having a redistribution layer connected with a pad electrode which is an uppermost wiring layer, a dummy pattern is arranged in a region closer to a scribe region than the redistribution layer.

公开(公告)号：US20180197753A1

公开(公告)日：2018-07-12

申请号：US15915746

申请日：2018-03-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masahiro MATSUMOTO ,  Kazuyoshi MAEKAWA ,  Yuichi KAWANO

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/4817 ,  H01L21/76852 ,  H01L23/3121 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2221/1078 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05008 ,  H01L2224/05075 ,  H01L2224/05548 ,  H01L2224/05664 ,  H01L2224/0612 ,  H01L2224/131 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a pad electrode formed at the uppermost layer of a plurality of wiring layers, a surface protective film having an opening over the pad electrode, a redistribution line being formed over the surface protective film and having an upper surface and a side surface, a sidewall barrier film comprising an insulating film covering the side surface and exposing the upper surface of the redistribution line, and a cap metallic film covering the upper surface of the redistribution line. Then the upper surface and side surface of the redistribution line are covered with the cap metallic film or the sidewall barrier film and the cap metallic film and the sidewall barrier film have an overlapping section.

公开(公告)号：US20150357400A1

公开(公告)日：2015-12-10

申请号：US14711471

申请日：2015-05-13

Applicant: Renesas Electronics Corporation

Inventor： Takahisa FURUHASHI ,  Masahiro MATSUMOTO

IPC: H01L49/02 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06

CPC classification number: H01L23/53223 ,  H01L23/53219 ,  H01L27/0629 ,  H01L27/14636 ,  H01L27/14643 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a capacitor, which provides enhanced reliability. A wiring and a capacitor are formed over an interlayer insulating film overlying a semiconductor substrate and another interlayer insulating film is formed over the interlayer insulating film so as to cover the wiring and capacitor. The capacitor includes a lower electrode overlying the interlayer insulating film, an upper electrode overlying the interlayer insulating film to cover the lower electrode at least partially, and a capacitive insulating film interposed between the lower and upper electrodes. The upper electrode and the wiring are formed from a conductive film pattern in the same layer. A plug is located under, and electrically coupled to, the lower electrode and another plug is located over the upper electrode's portion not overlapping the lower electrode in plan view and electrically coupled to the upper electrode. Another plug is located over, and electrically coupled to, the wiring.

Abstract translation: 一种具有电容器的半导体器件，其提供增强的可靠性。 在覆盖半导体衬底的层间绝缘膜上形成布线和电容器，并且在层间绝缘膜上形成另一层间绝缘膜，以覆盖布线和电容器。 电容器包括覆盖层间绝缘膜的下电极，覆盖层间绝缘膜以至少部分覆盖下电极的上电极以及置于下电极和上电极之间的电容绝缘膜。 上电极和布线由同一层中的导电膜图案形成。 插头位于下电极下方并电耦合，并且另一个插头位于上电极部分上方，在平面图中不与下电极重叠，并电耦合到上电极。 另一个插头位于布线上方并电耦合到布线上。

公开(公告)号：US20230215784A1

公开(公告)日：2023-07-06

申请号：US18182780

申请日：2023-03-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masahiro MATSUMOTO ,  Masahiko FUJISAWA ,  Akihiko OSAKI ,  Atsushi ISHII

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L23/5226 ,  H01L21/768

Abstract: A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

公开(公告)号：US20200211931A1

公开(公告)日：2020-07-02

申请号：US16811846

申请日：2020-03-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masahiro MATSUMOTO ,  Masahiko FUJISAWA ,  Akihiko OSAKI ,  Atsushi ISHII

IPC: H01L23/495 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L23/31

Abstract: A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to apart of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

公开(公告)号：US20170372996A1

公开(公告)日：2017-12-28

申请号：US15621745

申请日：2017-06-13

Applicant: Renesas Electronics Corporation

Inventor： Masahiro MATSUMOTO ,  Akira Yajima ,  Kazuyoshi Maekawa

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A bonding pad of a semiconductor chip in a QFP includes, in its exposed portion, a via disposition area comprising: a first segment that connects a corner and a first point; a second segment that connects the corner and a second point; and an arc that connects the first point and the second point and forms a convex shape toward the corner. Further, in a plan view of the bonding pad, at least a part of a via is disposed so as to overlap with the via disposition area.

公开(公告)号：US20160181184A1

公开(公告)日：2016-06-23

申请号：US14943900

申请日：2015-11-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masahiro MATSUMOTO ,  Kazuyoshi MAEKAWA ,  Yuichi KAWANO

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L21/4817 ,  H01L21/76852 ,  H01L23/3121 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2221/1078 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05008 ,  H01L2224/05075 ,  H01L2224/05548 ,  H01L2224/05664 ,  H01L2224/0612 ,  H01L2224/131 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a pad electrode formed at the uppermost layer of a plurality of wiring layers, a surface protective film having an opening over the pad electrode, a redistribution line being formed over the surface protective film and having an upper surface and a side surface, a sidewall barrier film comprising an insulating film covering the side surface and exposing the upper surface of the redistribution line, and a cap metallic film covering the upper surface of the redistribution line. Then the upper surface and side surface of the redistribution line are covered with the cap metallic film or the sidewall barrier film and the cap metallic film and the sidewall barrier film have an overlapping section.

Abstract translation: 本发明使得可以提高半导体器件的可靠性。 半导体器件在半导体衬底上具有形成在多个布线层的最上层的焊盘电极，在焊盘电极上具有开口的表面保护膜，在该表面保护膜上形成再分配线，并具有 上表面和侧表面，侧壁阻挡膜，其包括覆盖侧表面并暴露再分布线的上表面的绝缘膜，以及覆盖再分布线的上表面的帽金属膜。 然后再分配线的上表面和侧表面被盖金属膜或侧壁阻挡膜覆盖，并且帽金属膜和侧壁阻挡膜具有重叠部分。