公开(公告)号：US10236371B2

公开(公告)日：2019-03-19

申请号：US15403539

申请日：2017-01-11

Applicant: Renesas Electronics Corporation

Inventor： Tohru Kawai ,  Yasutaka Nakashiba ,  Yutaka Akiyama

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L27/07 ,  H01L29/06 ,  H01L29/10 ,  H01L23/495 ,  H01L23/522 ,  H01L23/00

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

公开(公告)号：US09871036B2

公开(公告)日：2018-01-16

申请号：US14209384

申请日：2014-03-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba ,  Yutaka Akiyama

IPC: H01L21/50 ,  H01L23/495 ,  H01L27/12 ,  H01L25/16 ,  H01L27/06 ,  H01L23/522

CPC classification number: H01L27/0688 ,  H01L23/49541 ,  H01L23/5227 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014

Abstract: A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit.

公开(公告)号：US09606012B2

公开(公告)日：2017-03-28

申请号：US14244820

申请日：2014-04-03

Applicant: Renesas Electronics Corporation

Inventor： Yutaka Akiyama ,  Yasutaka Nakashiba

IPC: H01L29/84 ,  G01L9/00 ,  H01L41/113

CPC classification number: G01L9/005 ,  G01L9/0055 ,  H01L29/84 ,  H01L41/113

Abstract: An object of the present invention is to suppress an error in the value detected by a pressure sensor, which may be caused when environmental temperature varies. A semiconductor substrate has a first conductivity type. A semiconductor layer is formed over a first surface of the semiconductor substrate. Each of resistance parts has a second conductivity type, and is formed in the semiconductor layer. The resistance parts are spaced apart from each other. A separation region is a region of the first conductivity type formed in the semiconductor layer, and electrically separates the resistance parts from each other. A depressed portion is formed in a second surface of the semiconductor substrate, and overlaps the resistance parts, when viewed planarly. The semiconductor layer is an epitaxial layer.

公开(公告)号：US09117903B2

公开(公告)日：2015-08-25

申请号：US14204145

申请日：2014-03-11

Applicant: Renesas Electronics Corporation

Inventor： Akihiro Shimomura ,  Yutaka Akiyama ,  Saya Shimomura ,  Yasutaka Nakashiba

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/808 ,  H01L29/40 ,  H01L29/739

CPC classification number: H01L29/7827 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083

Abstract: A buried layer of a second conductivity type and a lower layer of a second conductivity type are formed in a drift layer. A boundary insulating film is formed in the boundary between the lateral portion of the buried layer of a second conductivity type and the drift layer. The lower layer of a second conductivity type is in contact with the lower end of the buried layer of a second conductivity type and the lower end of the boundary insulating film. The buried layer of a second conductivity type is electrically connected to a source electrode. A high-concentration layer of a second conductivity type is formed in the surface layer of the buried layer of a second conductivity type.

Abstract translation: 在漂移层中形成第二导电类型的掩埋层和第二导电类型的下层。 边界绝缘膜形成在第二导电类型的掩埋层的横向部分与漂移层之间的边界中。 第二导电类型的下层与第二导电类型的掩埋层的下端和边界绝缘膜的下端接触。 第二导电类型的掩埋层与源电极电连接。 在第二导电类型的掩埋层的表面层中形成第二导电类型的高浓度层。

公开(公告)号：US10475918B2

公开(公告)日：2019-11-12

申请号：US16263256

申请日：2019-01-31

Applicant: Renesas Electronics Corporation

Inventor： Tohru Kawai ,  Yasutaka Nakashiba ,  Yutaka Akiyama

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L27/07 ,  H01L29/06 ,  H01L29/10 ,  H01L23/495 ,  H01L23/522 ,  H01L23/482 ,  H01L23/00

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

公开(公告)号：US09564426B2

公开(公告)日：2017-02-07

申请号：US14931991

申请日：2015-11-04

Applicant: Renesas Electronics Corporation

Inventor： Tohru Kawai ,  Yasutaka Nakashiba ,  Yutaka Akiyama

IPC: H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L27/07 ,  H01L23/00

CPC classification number: H01L29/7813 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0733 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract translation: 提高半导体器件的性能而不增加半导体芯片的面积尺寸。 例如，功率晶体管的源电极和电容器元件的上电极具有重叠部分。 换句话说，电容器元件的上电极通过电容器绝缘膜形成在功率晶体管的源极上。 也就是说，功率晶体管和电容器元件以半导体芯片的厚度方向层叠的方式配置。 结果，可以在抑制半导体芯片的平面尺寸的增加的同时添加电耦合到功率晶体管的电容器元件。

公开(公告)号：US20140264722A1

公开(公告)日：2014-09-18

申请号：US14209384

申请日：2014-03-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Yutaka Akiyama

IPC: H01L27/12

CPC classification number: H01L27/0688 ,  H01L23/49541 ,  H01L23/5227 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014

Abstract: A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit.

Abstract translation: 半导体芯片包括具有不同参考电位的第一电路和第二电路。 作为第一电路的基准电位的第一电位通过多个引线端子中的任一个施加到半导体芯片，作为第二电路的基准电位的第二电位通过多个引线端子中的任一个施加到半导体芯片 。 半导体芯片的基板具有其中掩埋绝缘层和第一导电类型的半导体层层叠在诸如SOI衬底的半导体衬底上的结构。 通过管芯焊盘和用于衬底电位的引线端子将固定电位施加到半导体衬底。 通过与第一电路的参考电位和第二电路的参考电位的不同路径将固定电位施加到半导体芯片。

公开(公告)号：US09385230B2

公开(公告)日：2016-07-05

申请号：US14804819

申请日：2015-07-21

Applicant: Renesas Electronics Corporation

Inventor： Akihiro Shimomura ,  Yutaka Akiyama ,  Saya Shimomura ,  Yasutaka Nakashiba

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/808 ,  H01L29/40 ,  H01L29/739 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083

Abstract: A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film.

Abstract translation: 一种半导体器件，包括第一导体层，形成在第一导体层上的第二导体层，形成在第二导体层上的第三导体层，通过第三导体层并形成在第二导体层中的栅极沟槽， 形成在栅极沟槽的内壁上的第一绝缘膜，形成在栅极沟槽的内壁上的第二绝缘膜，形成在栅极沟槽中的第一掩埋导体层，形成在栅极沟槽中的栅电极，第四绝缘膜 在第一掩埋导体层的下端形成的第二导电类型的导体层和栅极沟槽的下端，以及形成在第三导体层上的第一导电类型的第五导电层。 第一绝缘膜比第二绝缘膜厚。

公开(公告)号：US20140312440A1

公开(公告)日：2014-10-23

申请号：US14244820

申请日：2014-04-03

Applicant: Renesas Electronics Corporation

Inventor： Yutaka Akiyama ,  Yasutaka Nakashiba

IPC: G01L1/22

CPC classification number: G01L9/005 ,  G01L9/0055 ,  H01L29/84 ,  H01L41/113

Abstract: An object of the present invention is to suppress an error in the value detected by a pressure sensor, which may be caused when environmental temperature varies. A semiconductor substrate has a first conductivity type. A semiconductor layer is formed over a first surface of the semiconductor substrate. Each of resistance parts has a second conductivity type, and is formed in the semiconductor layer. The resistance parts are spaced apart from each other. A separation region is a region of the first conductivity type formed in the semiconductor layer, and electrically separates the resistance parts from each other. A depressed portion is formed in a second surface of the semiconductor substrate, and overlaps the resistance parts, when viewed planarly. The semiconductor layer is an epitaxial layer.

Abstract translation: 本发明的目的是抑制当环境温度变化时可能引起的压力传感器检测到的值的误差。 半导体衬底具有第一导电类型。 在半导体衬底的第一表面上形成半导体层。 每个电阻部分具有第二导电类型，并且形成在半导体层中。 电阻部分彼此间隔开。 分离区域是在半导体层中形成的第一导电类型的区域，并且使电阻部分彼此电分离。 在半导体衬底的第二表面中形成凹陷部分，并且当平面地观察时，与电阻部分重叠。 半导体层是外延层。