公开(公告)号：US20080179661A1

公开(公告)日：2008-07-31

申请号：US11865796

申请日：2007-10-02

申请人： Ralf Richter ,  Martin Gerhardt ,  Martin Mazur ,  Joerg Hohage

发明人： Ralf Richter ,  Martin Gerhardt ,  Martin Mazur ,  Joerg Hohage

IPC分类号： H01L29/78 ,  H01L21/469

CPC分类号： H01L29/7833 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/7843

摘要： By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.

摘要翻译： 通过在对具有不同的本征应力的介电衬垫进行图案化之后形成附加的应力介电材料，可以获得在晶体管中性能的显着提高，同时在高比例尺度的半导体器件中形成各个接触开口期间基本上不会构图不均匀性。 附加介电层可以被提供任何类型的固有应力，而不管先前选择的图案化序列如何。

公开(公告)号：US07994059B2

公开(公告)日：2011-08-09

申请号：US11865796

申请日：2007-10-02

申请人： Ralf Richter ,  Martin Gerhardt ,  Martin Mazur ,  Joerg Hohage

发明人： Ralf Richter ,  Martin Gerhardt ,  Martin Mazur ,  Joerg Hohage

IPC分类号： H01L21/331

CPC分类号： H01L29/7833 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/7843

摘要： By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.

摘要翻译： 通过在对具有不同的本征应力的介电衬垫进行图案化之后形成附加的应力介电材料，可以获得在晶体管中性能的显着提高，同时在高比例尺度的半导体器件中形成各个接触开口期间基本上不会构图不均匀性。 附加介电层可以被提供任何类型的固有应力，而不管先前选择的图案化序列如何。

公开(公告)号：US20080081480A1

公开(公告)日：2008-04-03

申请号：US11742878

申请日：2007-05-01

申请人： Kai Frohberg ,  Volker Grimm ,  Sven Mueller ,  Matthias Lehr ,  Ralf Richter ,  Jochen Klais ,  Martin Mazur ,  Heike Salz ,  Joerg Hohage ,  Matthias Schaller

发明人： Kai Frohberg ,  Volker Grimm ,  Sven Mueller ,  Matthias Lehr ,  Ralf Richter ,  Jochen Klais ,  Martin Mazur ,  Heike Salz ,  Joerg Hohage ,  Matthias Schaller

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

摘要： By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

摘要翻译： 通过进行等离子体处理以有效地密封包含氮化硅的应力介电层的表面，可以实现在接触开口的图案化期间提高的性能，因为在所选择的图形化应力层的选择性图案化期间可以显着降低氮诱导的抗蚀剂中毒 不同类型的内在应力。

公开(公告)号：US07938973B2

公开(公告)日：2011-05-10

申请号：US11733350

申请日：2007-04-10

申请人： Ralf Richter ,  Joerg Hohage ,  Martin Mazur

发明人： Ralf Richter ,  Joerg Hohage ,  Martin Mazur

IPC分类号： H01B13/00

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/76802

摘要： By incorporating a material exhibiting a high adhesion on chamber walls of a process chamber during sputter etching, the defect rate in a patterning sequence on the basis of an ARC layer may be significantly reduced, since the adhesion material may be reliably exposed during a sputter preclean process. The corresponding adhesion layer may be positioned within the ARC layer stack so as to be reliably consumed, at least partially, while nevertheless providing the required optical characteristics. Hence, a low defect rate in combination with a high process efficiency may be achieved.

摘要翻译： 通过在溅射蚀刻期间结合在处理室的室壁上表现出高粘附性的材料，可以显着地减少基于ARC层的图案化顺序中的缺陷率，因为粘合材料可以在溅射预清洗期间可靠地暴露 处理。 相应的粘合层可以定位在ARC层堆叠内，以便至少部分地可靠地消耗，同时仍然提供所需的光学特性。 因此，可以实现低缺陷率与高工艺效率的组合。

公开(公告)号：US07550396B2

公开(公告)日：2009-06-23

申请号：US11742878

申请日：2007-05-01

申请人： Kai Frohberg ,  Volker Grimm ,  Sven Mueller ,  Matthias Lehr ,  Ralf Richter ,  Jochen Klais ,  Martin Mazur ,  Heike Salz ,  Joerg Hohage ,  Matthias Schaller

发明人： Kai Frohberg ,  Volker Grimm ,  Sven Mueller ,  Matthias Lehr ,  Ralf Richter ,  Jochen Klais ,  Martin Mazur ,  Heike Salz ,  Joerg Hohage ,  Matthias Schaller

IPC分类号： H01L21/461

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

摘要： By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

摘要翻译： 通过进行等离子体处理以有效地密封包含氮化硅的应力介电层的表面，可以实现在接触开口的图案化期间提高的性能，因为在所选择的图形化应力层的选择性图案化期间可以显着降低氮诱导的抗蚀剂中毒 不同类型的内在应力。

公开(公告)号：US20080078738A1

公开(公告)日：2008-04-03

申请号：US11733350

申请日：2007-04-10

申请人： Ralf Richter ,  Joerg Hohage ,  Martin Mazur

发明人： Ralf Richter ,  Joerg Hohage ,  Martin Mazur

IPC分类号： H01B13/00

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/76802

摘要： By incorporating a material exhibiting a high adhesion on chamber walls of a process chamber during sputter etching, the defect rate in a patterning sequence on the basis of an ARC layer may be significantly reduced, since the adhesion material may be reliably exposed during a sputter preclean process. The corresponding adhesion layer may be positioned within the ARC layer stack so as to be reliably consumed, at least partially, while nevertheless providing the required optical characteristics. Hence, a low defect rate in combination with a high process efficiency may be achieved.

摘要翻译： 通过在溅射蚀刻期间结合在处理室的室壁上表现出高粘附性的材料，可以显着地减少基于ARC层的图案化顺序中的缺陷率，因为粘合材料可以在溅射预清洗期间可靠地暴露 处理。 相应的粘合层可以定位在ARC层堆叠内，以便至少部分地可靠地消耗，同时仍然提供所需的光学特性。 因此，可以实现低缺陷率与高工艺效率的组合。

公开(公告)号：US20100330808A1

公开(公告)日：2010-12-30

申请号：US12824534

申请日：2010-06-28

申请人： Ralf Richter ,  Frank Seliger ,  Martin Mazur

发明人： Ralf Richter ,  Frank Seliger ,  Martin Mazur

IPC分类号： H01L21/311

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

摘要： In a replacement gate approach, the dielectric cap layers of the gate electrode structures are removed in a separate removal process, such as a plasma assisted etch process, in order to provide superior process conditions during the subsequent planarization of the interlayer dielectric material for exposing the sacrificial gate material. Due to the superior process conditions, the selective removal of the sacrificial gate material may be accomplished with enhanced uniformity, thereby also contributing to superior stability of transistor characteristics.

摘要翻译： 在替代栅极方法中，在单独的去除工艺（例如等离子体辅助蚀刻工艺）中去除栅电极结构的电介质盖层，以便在层间电介质材料随后的平坦化期间提供优异的工艺条件， 牺牲栅材料。 由于优异的工艺条件，牺牲栅极材料的选择性去除可以通过增强的均匀性来实现，从而也有助于晶体管特性的优异的稳定性。

公开(公告)号：US08258062B2

公开(公告)日：2012-09-04

申请号：US12824534

申请日：2010-06-28

申请人： Ralf Richter ,  Frank Seliger ,  Martin Mazur

发明人： Ralf Richter ,  Frank Seliger ,  Martin Mazur

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

摘要： In a replacement gate approach, the dielectric cap layers of the gate electrode structures are removed in a separate removal process, such as a plasma assisted etch process, in order to provide superior process conditions during the subsequent planarization of the interlayer dielectric material for exposing the sacrificial gate material. Due to the superior process conditions, the selective removal of the sacrificial gate material may be accomplished with enhanced uniformity, thereby also contributing to superior stability of transistor characteristics.

摘要翻译： 在替代栅极方法中，在单独的去除工艺（例如等离子体辅助蚀刻工艺）中去除栅电极结构的电介质盖层，以便在层间电介质材料随后的平坦化期间提供优异的工艺条件， 牺牲栅材料。 由于优异的工艺条件，牺牲栅极材料的选择性去除可以通过增强的均匀性来实现，从而也有助于晶体管特性的优异的稳定性。

公开(公告)号：US09281200B2

公开(公告)日：2016-03-08

申请号：US13189997

申请日：2011-07-25

申请人： Hans-Juergen Thees ,  Sven Beyer ,  Martin Mazur ,  Steffen Laufer

发明人： Hans-Juergen Thees ,  Sven Beyer ,  Martin Mazur ,  Steffen Laufer

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/49

CPC分类号： H01L21/28123 ,  H01L21/265 ,  H01L21/28035 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/4916

摘要： When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.

摘要翻译： 当形成晶体管的复杂的基于半导体的栅极电极结构时，一种类型的栅极电极结构的预掺杂可以在通过使用适当的掩模或填充材料覆盖活性区域并使用 光刻面具 以这种方式，在选择适当的图案化状态方面提供了高度的柔性，同时获得了任何类型的栅电极结构的均匀和优异的横截面形状。

公开(公告)号：US20090274981A1

公开(公告)日：2009-11-05

申请号：US12113559

申请日：2008-05-01

申请人： Uwe Griebenow ,  Martin Mazur ,  Wolfram Grundke ,  Andre Poock

发明人： Uwe Griebenow ,  Martin Mazur ,  Wolfram Grundke ,  Andre Poock

IPC分类号： G03F7/20

CPC分类号： G01N21/956 ,  G01N2021/95676 ,  G03F1/84

摘要： Mask defects, such as crystal growth defects and the like, may be efficiently detected and estimated at an early stage of their development by generating test images of the mask under consideration and inspecting the images on the basis of wafer inspection techniques in order to identify repeatedly occurring defects. In some illustrative embodiments, the exposure process for generating the mask images may be performed on the basis of different exposure parameters, such as exposure doses, in order to enhance the probability of detecting defects and also estimating the effect thereof depending on the varying exposure parameters. Consequently, increased reliability may be achieved compared to conventional direct mask inspection techniques.

摘要翻译： 通过产生所考虑的掩模的测试图像并且在晶片检查技术的基础上检查图像以便重复地识别掩模缺陷，例如晶体生长缺陷等，可以在其显影的早期阶段被有效地检测和估计 发生缺陷。 在一些说明性实施例中，用于产生掩模图像的曝光过程可以基于不同的曝光参数（例如曝光剂量）来执行，以增强检测缺陷的可能性，并且还根据变化的曝光参数来估计其效果 。 因此，与传统的直接掩模检查技术相比，可以实现增加的可靠性。