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    Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan
    5.
    发明授权
    Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan 失效
    通过同步时钟停止和扫描来调试集成电路芯片的方法和装置

    公开(公告)号：US08140925B2

    公开(公告)日：2012-03-20

    申请号：US11768791

    申请日：2007-06-26

    申请人： Ralph E. Bellofatto ,  Matthew R. Ellavsky ,  Alan G. Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Lance G. Hehenberger ,  Martin Ohmacht

    发明人： Ralph E. Bellofatto ,  Matthew R. Ellavsky ,  Alan G. Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Lance G. Hehenberger ,  Martin Ohmacht

    IPC分类号： G01R31/28 ,  G06F1/12

    CPC分类号： G06F11/2236

    摘要： An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

    摘要翻译： 一种用于评估电子或集成电路（IC）的状态的装置和方法，每个IC包括用于控制IC子单元的操作的一个或多个处理器元件，以及每个支持多个时钟域的IC。 该方法包括：根据确定的定时配置，产生与一个或多个IC子单元相对应的用于开始一个或多个IC子单元的操作的同步的使能信号组; 计数，响应于同步的一组使能信号的一个信号，多个主处理器IC时钟周期; 并且在获得期望的时钟周期数时，产生用于每个唯一频率时钟域的停止信号以同步地停止每个相应频率时钟域的功能时钟; 并且在确定性地同时停止所有频率时钟域上的所有片上功能时钟时，以期望的IC芯片状态扫描数据值。 该装置和方法使得能够使用片上电路和软件的组合来构建运行中的IC芯片的状态的任何部分的逐周期视图。

    METHOD AND APPARATUS TO DEBUG AN INTEGRATED CIRCUIT CHIP VIA SYNCHRONOUS CLOCK STOP AND SCAN
    6.
    发明申请
    METHOD AND APPARATUS TO DEBUG AN INTEGRATED CIRCUIT CHIP VIA SYNCHRONOUS CLOCK STOP AND SCAN 失效
    通过同步时钟停止和扫描来调试集成电路芯片的方法和设备

    公开(公告)号：US20090006894A1

    公开(公告)日：2009-01-01

    申请号：US11768791

    申请日：2007-06-26

    申请人： Ralph E. Bellofatto ,  Matthew R. Ellavsky ,  Alan G. Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Lance G. Hehenberger ,  Martin Ohmacht

    发明人： Ralph E. Bellofatto ,  Matthew R. Ellavsky ,  Alan G. Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Lance G. Hehenberger ,  Martin Ohmacht

    IPC分类号： G06F11/00

    CPC分类号： G06F11/2236

    摘要： An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

    摘要翻译： 一种用于评估电子或集成电路（IC）的状态的装置和方法，每个IC包括用于控制IC子单元的操作的一个或多个处理器元件，以及每个支持多个时钟域的IC。 该方法包括：根据确定的定时配置，产生与一个或多个IC子单元相对应的用于开始一个或多个IC子单元的操作的同步的使能信号组; 计数，响应于同步的一组使能信号的一个信号，多个主处理器IC时钟周期; 并且在获得期望的时钟周期数时，产生用于每个唯一频率时钟域的停止信号以同步地停止每个相应频率时钟域的功能时钟; 并且在确定性地同时停止所有频率时钟域上的所有片上功能时钟时，以期望的IC芯片状态扫描数据值。 该装置和方法使得能够使用片上电路和软件的组合来构建运行中的IC芯片的状态的任何部分的逐周期视图。