公开(公告)号：US20050221001A1

公开(公告)日：2005-10-06

申请号：US10814713

申请日：2004-03-31

申请人： Raymond Joe ,  John Gumpher ,  Anthony Dip

发明人： Raymond Joe ,  John Gumpher ,  Anthony Dip

IPC分类号： C23C16/34 ,  C23C16/44 ,  H01L21/318 ,  C23C16/00 ,  B32B9/00

CPC分类号： C23C16/4404 ,  H01L21/3185

摘要： A method for extending time between chamber cleaning processes in a process chamber of a processing system. A particle-reducing film is formed on a chamber component in the process chamber to reduce particle formation in the process chamber during substrate processing, at least one substrate is introduced into the process chamber, a manufacturing process is performed in the process chamber, and the at least one substrate is removed from the process chamber. The particle-reducing film may be deposited on a clean chamber component or on a material deposit formed on a chamber component. Alternatively, the particle-reducing film may be formed by chemically modifying at least a portion of a material deposit on a chamber component. The particle-reducing film may be formed after each manufacturing process or at selected intervals after multiple manufacturing processes.

摘要翻译： 一种用于在处理系统的处理室中延长室清洁过程之间的时间的方法。 在处理室中的腔室部件上形成颗粒减少膜，以减少衬底处理期间处理室中的颗粒形成，至少一个衬底被引入到处理室中，在处理室中执行制造工艺， 从处理室移除至少一个基板。 颗粒减少膜可以沉积在清洁室部件上或者形成在室部件上的材料沉积物上。 或者，可以通过化学改变室内部件上的材料沉积物的至少一部分来形成颗粒减少膜。 减少颗粒的膜可以在每个制造过程之后形成，或者在多个制造过程之后以选定的间隔形成。

公开(公告)号：US07604841B2

公开(公告)日：2009-10-20

申请号：US10814713

申请日：2004-03-31

申请人： Raymond Joe ,  John Gumpher ,  Anthony Dip

发明人： Raymond Joe ,  John Gumpher ,  Anthony Dip

IPC分类号： C23C16/30

CPC分类号： C23C16/4404 ,  H01L21/3185

摘要： A method for extending time between chamber cleaning processes in a process chamber of a processing system. A particle-reducing film is formed on a chamber component in the process chamber to reduce particle formation in the process chamber during substrate processing, at least one substrate is introduced into the process chamber, a manufacturing process is performed in the process chamber, and the at least one substrate is removed from the process chamber. The particle-reducing film may be deposited on a clean chamber component or on a material deposit formed on a chamber component. Alternatively, the particle-reducing film may be formed by chemically modifying at least a portion of a material deposit on a chamber component. The particle-reducing film may be formed after each manufacturing process or at selected intervals after multiple manufacturing processes.

摘要翻译： 一种用于在处理系统的处理室中延长室清洁过程之间的时间的方法。 在处理室中的腔室部件上形成颗粒减少膜，以减少衬底处理期间处理室中的颗粒形成，至少一个衬底被引入到处理室中，在处理室中执行制造工艺， 从处理室移除至少一个基板。 颗粒减少膜可以沉积在清洁室部件上或者形成在室部件上的材料沉积物上。 或者，可以通过化学改变室内部件上的材料沉积物的至少一部分来形成颗粒减少膜。 减少颗粒的膜可以在每个制造过程之后形成，或者在多个制造过程之后以选定的间隔形成。

公开(公告)号：US20080169534A1

公开(公告)日：2008-07-17

申请号：US11622204

申请日：2007-01-11

申请人： Anthony Dip ,  John Gumpher ,  Allen John Leith ,  Seungho Oh

发明人： Anthony Dip ,  John Gumpher ,  Allen John Leith ,  Seungho Oh

IPC分类号： H01L21/36 ,  H01L29/06

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0262 ,  H01L21/02639

摘要： A method is provided for reduced defect such as void free or reduced void Si or SiGe deposition in a micro-feature on a patterned substrate. The micro-feature includes a sidewall and the patterned substrate contains an isolation layer on the field area and on the sidewall and bottom of the micro-feature. The method includes forming a Si or SiGe seed layer at the bottom of the micro-feature, and at least partially filling the micro-feature from the bottom up by selectively growing Si or SiGe onto the Si or SiGe seed layer. According to one embodiment, the Si or SiGe seed layer is formed by depositing a conformal Si or SiGe layer onto the patterned substrate, removing the Si or SiGe layer from the field area, heat treating the Si or SiGe layer in the presence of H2 gas to transfer at least a portion of the Si or SiGe layer from the sidewall to the bottom of the micro-feature, and etching Si or SiGe residue from the field area and the sidewall.

摘要翻译： 提供了一种减少缺陷的方法，例如在图案化衬底上的微特征中的无空隙或减少的空隙Si或SiGe沉积。 微型特征包括侧壁，并且图案化衬底在场区域和微特征的侧壁和底部上包含隔离层。 该方法包括在微特征的底部形成Si或SiGe种子层，并且通过在Si或SiGe种子层上选择性地生长Si或SiGe，从底部至少部分地填充微特征。 根据一个实施例，Si或SiGe种子层通过将沉积的Si或SiGe层沉积在图案化的衬底上，从场区去除Si或SiGe层而形成，在H区存在下热处理Si或SiGe层， 从而将Si或SiGe层的至少一部分从侧壁传递到微特征的底部，并且从场区域和侧壁蚀刻Si或SiGe残留物。

公开(公告)号：US08263474B2

公开(公告)日：2012-09-11

申请号：US11622204

申请日：2007-01-11

申请人： Anthony Dip ,  John Gumpher ,  Allen John Leith ,  Seungho Oh

发明人： Anthony Dip ,  John Gumpher ,  Allen John Leith ,  Seungho Oh

IPC分类号： H01L21/76

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0262 ,  H01L21/02639

摘要： A method is provided for reduced defect such as void free or reduced void Si or SiGe deposition in a micro-feature on a patterned substrate. The micro-feature includes a sidewall and the patterned substrate contains an isolation layer on the field area and on the sidewall and bottom of the micro-feature. The method includes forming a Si or SiGe seed layer at the bottom of the micro-feature, and at least partially filling the micro-feature from the bottom up by selectively growing Si or SiGe onto the Si or SiGe seed layer. According to one embodiment, the Si or SiGe seed layer is formed by depositing a conformal Si or SiGe layer onto the patterned substrate, removing the Si or SiGe layer from the field area, heat treating the Si or SiGe layer in the presence of H2 gas to transfer at least a portion of the Si or SiGe layer from the sidewall to the bottom of the micro-feature, and etching Si or SiGe residue from the field area and the sidewall.

摘要翻译： 提供了一种减少缺陷的方法，例如在图案化衬底上的微特征中的无空隙或减少的空隙Si或SiGe沉积。 微型特征包括侧壁，并且图案化衬底在场区域和微特征的侧壁和底部上包含隔离层。 该方法包括在微特征的底部形成Si或SiGe种子层，并且通过在Si或SiGe种子层上选择性地生长Si或SiGe，从底部至少部分地填充微特征。 根据一个实施例，Si或SiGe种子层通过将沉积Si或SiGe层保护到图案化衬底上而形成，从场区去除Si或SiGe层，在H 2气体存在下热处理Si或SiGe层 以将Si或SiGe层的至少一部分从侧壁传递到微特征的底部，并且从场区域和侧壁蚀刻Si或SiGe残留物。

公开(公告)号：US08466045B2

公开(公告)日：2013-06-18

申请号：US12830210

申请日：2010-07-02

申请人： John Gumpher ,  Seungho Oh ,  Anthony Dip

发明人： John Gumpher ,  Seungho Oh ,  Anthony Dip

IPC分类号： H01L21/20

CPC分类号： H01L21/02661 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02664

摘要： A method for forming strained epitaxial carbon-doped silicon (Si) films, for example as raised source and drain regions for electronic devices. The method includes providing a structure having an epitaxial Si surface and a patterned film, non-selectively depositing a carbon-doped Si film onto the structure, the carbon-doped Si film containing an epitaxial carbon-doped Si film deposited onto the epitaxial Si surface and a non-epitaxial carbon-doped Si film deposited onto the patterned film, and non-selectively depositing a Si film on the carbon-doped Si film, the Si film containing an epitaxial Si film deposited onto the epitaxial carbon-doped Si film and a non-epitaxial Si film deposited onto the non-epitaxial carbon-doped Si film. The method further includes dry etching away the non-epitaxial Si film, the non-epitaxial carbon-doped Si film, and less than the entire epitaxial Si film to form a strained epitaxial carbon-doped Si film on the epitaxial Si surface.

摘要翻译： 用于形成应变外延碳掺杂硅（Si）膜的方法，例如用于电子器件的升高的源极和漏极区域。 该方法包括提供具有外延Si表面和图案化膜的结构，在结构上非选择性地沉积掺杂碳的Si膜，所述掺杂碳的Si膜含有沉积到外延Si表面上的外延碳掺杂的Si膜 以及沉积到图案化膜上的非外延碳掺杂Si膜，并且在掺碳的Si膜上非选择性地沉积Si膜，所述Si膜含有沉积到外延碳掺杂的Si膜上的外延Si膜，以及 沉积在非外延碳掺杂Si膜上的非外延Si膜。 该方法还包括干蚀刻去除非外延Si膜，非外延碳掺杂Si膜，并且小于整个外延Si膜以在外延Si表面上形成应变外延碳掺杂Si膜。

公开(公告)号：US20050048742A1

公开(公告)日：2005-03-03

申请号：US10647534

申请日：2003-08-26

申请人： Anthony Dip ,  Pradip Roy ,  Raymond Joe

发明人： Anthony Dip ,  Pradip Roy ,  Raymond Joe

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/302 ,  H01L21/322 ,  H01L21/461

CPC分类号： H01L21/28238 ,  H01L21/02049 ,  H01L21/02052 ,  H01L21/28255

摘要： This invention provides a method for modifying the surface properties of a Si or Si alloy substrate by performing repeated etch-grow cycles of thermal oxide to yield a more defect free substrate with a more uniform nucleating surface which provides an improved interface for dielectric formation. Additionally, this method of processing does not expose the substrate to ambient atmosphere and preserves the improved surface until subsequent processing steps are performed.

摘要翻译： 本发明提供了一种通过进行热氧化物的重复蚀刻生长循环来改善Si或Si合金衬底的表面性质的方法，以产生具有更均匀的成核表面的更无缺陷的衬底，其提供用于电介质形成的改进的界面。 此外，这种处理方法不会使衬底暴露于环境大气中并保留改进的表面，直到执行后续的处理步骤。

公开(公告)号：US07165011B1

公开(公告)日：2007-01-16

申请号：US11217230

申请日：2005-09-01

申请人： Sanjeev Kaushal ,  Pradeep Pandey ,  Kenji Sugishima ,  Anthony Dip ,  David Smith ,  Raymond Joe ,  Sundar Gandhi

发明人： Sanjeev Kaushal ,  Pradeep Pandey ,  Kenji Sugishima ,  Anthony Dip ,  David Smith ,  Raymond Joe ,  Sundar Gandhi

IPC分类号： G06F11/30 ,  G06F15/00

CPC分类号： H01L22/10 ,  G05B23/0254 ,  H01L21/67248

摘要： A method of monitoring a thermal processing system in real-time using a built-in self test (BIST) table that includes positioning a plurality of wafers in a processing chamber in the thermal processing system; executing a real-time dynamic model to generate a predicted dynamic process response for the processing chamber during the processing time; creating a first measured dynamic process response; determining a dynamic estimation error using a difference between the predicted dynamic process response and the measured dynamic process response; and comparing the dynamic estimation error to operational thresholds established by one or more rules in the BIST table.

摘要翻译： 一种使用内置自检（BIST）表实时监测热处理系统的方法，其包括将多个晶片定位在热处理系统中的处理室中; 执行实时动态模型以在处理时间期间为处理室生成预测的动态过程响应; 创建第一个测量动态过程响应; 使用预测的动态过程响应和测量的动态过程响应之间的差来确定动态估计误差; 以及将动态估计误差与由BIST表中的一个或多个规则建立的操作阈值进行比较。

公开(公告)号：US20050199877A1

公开(公告)日：2005-09-15

申请号：US10797876

申请日：2004-03-10

申请人： Anthony Dip ,  Pradip Roy ,  Sanjeev Kaushal ,  Allen Leith ,  Seungho Oh ,  Raymond Joe

发明人： Anthony Dip ,  Pradip Roy ,  Sanjeev Kaushal ,  Allen Leith ,  Seungho Oh ,  Raymond Joe

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L29/12 ,  H01L21/36 ,  H01L21/3205

CPC分类号： H01L21/31604 ,  H01L21/02142 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/02362 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/3185 ,  Y10T29/41

摘要： A method for using a silicon germanium (SiGe) surface layer to integrate a high-k dielectric layer into a semiconductor device. The method forms a SiGe surface layer on a substrate and deposits a high-k dielectric layer on the SiGe surface layer. An oxide layer, located between the high-k dielectric layer and an unreacted portion of the SiGe surface layer, is formed during one or both of deposition of the high-k dielectric layer and an annealing process after deposition of the high-k dielectric layer. The method further includes forming an electrode layer on the high-k dielectric layer.

摘要翻译： 一种使用硅锗（SiGe）表面层将高k电介质层集成到半导体器件中的方法。 该方法在衬底上形成SiGe表面层，并在SiGe表面层上沉积高k电介质层。 在高k电介质层的沉积和沉积高k电介质层之间的退火工艺中的一个或两个期间，形成位于高k电介质层和SiGe表面层的未反应部分之间的氧化物层 。 该方法还包括在高k电介质层上形成电极层。

公开(公告)号：US06799940B2

公开(公告)日：2004-10-05

申请号：US10310141

申请日：2002-12-05

申请人： Raymond Joe ,  Anthony Dip

发明人： Raymond Joe ,  Anthony Dip

IPC分类号： B65G4907

CPC分类号： H01L21/68735 ,  H01L21/67109 ,  H01L21/67309 ,  H01L21/67346 ,  Y10S414/135 ,  Y10S414/137

摘要： A removable semiconductor wafer susceptor used for supporting a substrate during batch processing. The susceptor includes a flat circular central plane with a predetermined outer diameter. The susceptor is sized to fit within an inner diameter formed from wafer support ledges of a wafer transport container. The susceptor includes edges that are chamfered and rounded to lessen stress concentration at the edges. The susceptor is transported through processing by a sieving action of transport automation.

摘要翻译： 用于在批量处理期间支撑基板的可移除的半导体晶片基座。 基座包括具有预定外径的平圆形中心平面。 基座的尺寸设计成适合于由晶片运输容器的晶片支撑壁架形成的内径。 基座包括倒角和倒圆的边缘，以减少边缘处的应力集中。 感受器通过运输自动化的筛选动作运输。

公开(公告)号：US07022192B2

公开(公告)日：2006-04-04

申请号：US10233483

申请日：2002-09-04

申请人： Anthony Dip ,  Takanori Saito ,  Raymond Joe

发明人： Anthony Dip ,  Takanori Saito ,  Raymond Joe

IPC分类号： H01L21/00 ,  C23C16/00

CPC分类号： H01L21/67309 ,  Y10S206/832

摘要： A semiconductor wafer susceptor for batch substrate processing. The susceptor includes a central region in a primary plane and a plurality of flat annular extensions extending below the central region in a secondary plane. The primary and secondary planes are parallel to each other. An edge of the substrate overhangs the central region allowing no contact of the susceptor with the substrate edge.

摘要翻译： 用于批量衬底加工的半导体晶片基座。 基座包括主平面中的中心区域和在次平面内在中心区域下方延伸的多个平的环形延伸部。 主平面和次平面彼此平行。 衬底的边缘突出中心区域，允许基座与衬底边缘不接触。