公开(公告)号：US20130207252A1

公开(公告)日：2013-08-15

申请号：US13846730

申请日：2013-03-18

Applicant: Renesas Electronics Corporation

Inventor： Kuniharu MUTO ,  Toshiyuki HATA ,  Hiroshi SATO ,  Hiroi OKA ,  Osamu IKEDA

IPC: H01L23/495

CPC classification number: H01L23/49582 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/544 ,  H01L24/05 ,  H01L24/29 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/77 ,  H01L24/78 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L29/0615 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/40091 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/4912 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84205 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85214 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01054 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/83205 ,  H01L2924/206

Abstract: To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.

Abstract translation: 实现密封在其中的功率MOSFET的小型表面安装封装的导通电阻的降低。 硅芯片安装在与构成漏极引线的引线集成的管芯焊盘部分上。 硅芯片在其主表面上具有源极焊盘和栅极焊盘。 硅芯片的背面配置功率MOSFET的漏极，并通过Ag浆料粘合到芯片焊盘部分的上表面。 构成源极引线的引线通过Al带电耦合到源极焊盘，而构成栅极引线的引线通过Au线电耦合到栅极焊盘。