公开(公告)号：US20210111193A1

公开(公告)日：2021-04-15

申请号：US17003245

申请日：2020-08-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shibun TSUDA

IPC: H01L27/12 ,  H01L27/092 ,  H01L27/11 ,  H01L29/08 ,  H01L29/417 ,  H01L29/51 ,  H01L21/02 ,  H01L21/32 ,  H01L21/8238 ,  H01L21/84

Abstract: The first gate insulating film is an insulating film made of silicon oxide, and to which hafnium (Hf) is added without addition of aluminum (Al). Also, the second gate insulating film is an insulating film made of silicon oxide, and to which aluminum is added without addition of hafnium. The third gate insulating film is an insulating film made of silicon oxide, and to which aluminum is added. Further, the fourth gate insulating film is an insulating film made of silicon oxide, and to which hafnium is added. Accordingly, it is possible to reduce the power consumption of the semiconductor device.

公开(公告)号：US20200185394A1

公开(公告)日：2020-06-11

申请号：US16786176

申请日：2020-02-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shibun TSUDA ,  Tomohiro YAMASHITA

IPC: H01L27/1157 ,  H01L21/8234 ,  H01L27/11573 ,  H01L29/792 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/28

Abstract: When a memory cell is formed over a first fin and a low breakdown voltage transistor is formed over a second fin, the depth of a first trench for dividing the first fins in a memory cell region is made larger than that of a second trench for dividing the second fins in a logic region. Thereby, in the direction perpendicular to the upper surface of a semiconductor substrate, the distance between the upper surface of the first fin and the bottom surface of an element isolation region in the memory cell region becomes larger than that between the upper surface of the second fin and the bottom surface of the element isolation region in the logic region.

公开(公告)号：US20240290791A1

公开(公告)日：2024-08-29

申请号：US18433827

申请日：2024-02-06

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya YOSHIDA ,  Shibun TSUDA ,  Hideki MAKIYAMA

IPC: H01L27/12 ,  H01L21/265 ,  H01L21/84 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/26513 ,  H01L21/84 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/7838

Abstract: A low withstand voltage MISFET and a high withstand voltage MISFET are formed on an SOI substrate. An ON operation and an OFF operation of the low withstand voltage MISFET are controlled by a first gate potential to be supplied to a first gate electrode and a back gate potential to be supplied to a first well region. An ON operation and an OFF operation of the high withstand voltage MISFET are controlled by a second gate potential to be supplied to a second gate electrode in a state where a second well region is electrically floating. An absolute value of a second power supply potential to be supplied to a second impurity region is larger than an absolute value of a first power supply potential to be supplied to a first impurity region.

公开(公告)号：US20190164986A1

公开(公告)日：2019-05-30

申请号：US16130870

申请日：2018-09-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shibun TSUDA

IPC: H01L27/11563 ,  H01L27/088 ,  H01L29/66 ,  H01L29/792 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/04

Abstract: The performances of a semiconductor device are improved. A plurality of first gate patterns are formed over a fin of a part of a semiconductor substrate. A gate insulation film including a metal oxide film is formed between the adjacent first gate patterns. Then, a memory gate electrode is formed over the gate insulation film to fill between the adjacent first gate patterns. Then, the first gate patterns are selectively removed, to form a second gate pattern at the side surface of the memory gate electrode via the gate insulation film. Then, ions are implanted into the fin exposed from the memory gate electrode and the second gate pattern, to form an extension region in the fin. During formation of the extension region, the gate insulation film is not formed at the side surface of the fin, and hence ion implantation is not inhibited.

公开(公告)号：US20170200726A1

公开(公告)日：2017-07-13

申请号：US15366047

申请日：2016-12-01

Applicant: Renesas Electronics Corporation

Inventor： Shibun TSUDA ,  Tomohiro YAMASHITA

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: When a memory cell is formed over a first fin and a low breakdown voltage transistor is formed over a second fin, the depth of a first trench for dividing the first fins in a memory cell region is made larger than that of a second trench for dividing the second fins in a logic region. Thereby, in the direction perpendicular to the upper surface of a semiconductor substrate, the distance between the upper surface of the first fin and the bottom surface of an element isolation region in the memory cell region becomes larger than that between the upper surface of the second fin and the bottom surface of the element isolation region in the logic region.

公开(公告)号：US20230298889A1

公开(公告)日：2023-09-21

申请号：US17697418

申请日：2022-03-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shibun TSUDA

IPC: H01L21/027 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/0272 ,  H01L21/7624 ,  H01L21/31051 ,  H01L21/02126

Abstract: After a plurality of trenches is formed in an SOI substrate, a side surface of the insulating layer is retreated from a side surface of the semiconductor layer and a side surface of the semiconductor substrate. Next, the side surface of the insulating layer is covered with an organic film and also the side surface of the semiconductor layer is exposed from the organic film by performing an anisotropic etching process to the organic film embedded into an inside of each of the plurality of trenches. Next, each of the side surface of the semiconductor layer and the side surface of the semiconductor substrate is approached to the side surface of the insulating layer by performing an isotropic etching process. Further, after the organic film is removed, an oxidation treatment is performed to each of the side surface of the semiconductor layer and the side surface of the semiconductor substrate.

公开(公告)号：US20200211909A1

公开(公告)日：2020-07-02

申请号：US16719385

申请日：2019-12-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shibun TSUDA

IPC: H01L21/84 ,  H01L21/8234

Abstract: The reliability of the semiconductor device is suppressed from deteriorating. A first gate electrode is formed on the semiconductor layer SM located in the SOI region 1A of the substrate 1 having the semiconductor base material SB, the insulating layer BX, and the semiconductor layer SM via the first gate insulating film, a second gate electrode is formed on the semiconductor base material SB located in the first region 1Ba of the bulk region 1B and on which the epitaxial growth treatment is performed via the second gate insulating film, and a third gate electrode is formed on the semiconductor base material SB located in the second region 1Bb of the bulk region 1B and on which the epitaxial growth treatment is not performed via the third gate insulating film.

公开(公告)号：US20190148394A1

公开(公告)日：2019-05-16

申请号：US16243319

申请日：2019-01-09

Applicant: Renesas electronics Corporation

Inventor： Shibun TSUDA

IPC: H01L27/11568 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/423 ,  H01L29/792 ,  H01L27/11573 ,  H01L27/1157 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/11568 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7856 ,  H01L29/792

Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film having a first thickness over a main surface of a semiconductor substrate and then forming a second insulating film having a second thickness larger than the first thickness over the first insulating film, sequentially processing the second insulating film, the first insulating film, and the semiconductor substrate to form a plurality of trenches and to form a plurality of projecting portions which include portions of the semiconductor substrate extending in a first direction along the main surface of the semiconductor substrate and are spaced apart from each other in a second direction orthogonal to the first direction along the main surface of the semiconductor substrate, and depositing a third insulating film over the main surface of the semiconductor substrate such that the third insulating film is embedded in the trenches.

公开(公告)号：US20180012901A1

公开(公告)日：2018-01-11

申请号：US15498547

申请日：2017-04-27

Applicant: Renesas Electronics Corporation

Inventor： Shibun TSUDA

IPC: H01L29/792 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/762 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7856 ,  H01L29/792

Abstract: An improvement is achieved in the reliability of a semiconductor device. In a memory cell region, a plurality of fins are provided which are portions of a semiconductor substrate extending in an x-direction along a main surface of the semiconductor substrate and spaced apart from each other in a y-direction orthogonal to the x-direction along the main surface of the semiconductor substrate. Between the fins adjacent to each other in the y-direction, a portion of an upper surface of an isolation region is at a position higher than a surface obtained by connecting a position of the upper surface of the isolation region which is in contact with a side wall of one of the fins to a position of the upper surface of the isolation region which is in contact with a side wall of the other fin. In a cross section along the y-direction, the upper surface of the isolation region has a projecting shape.

公开(公告)号：US20190006382A1

公开(公告)日：2019-01-03

申请号：US16045183

申请日：2018-07-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yosuke TAKEUCHI ,  Eiji TSUKUDA ,  Kenichiro SONODA ,  Shibun TSUDA

IPC: H01L27/11573 ,  H01L29/423 ,  H01L29/792 ,  H01L29/78 ,  H01L27/11565

Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.