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106 条记录 (耗时 0.025 秒)

    High-K dielectric materials and processes for manufacturing them
    3.
    发明授权
    High-K dielectric materials and processes for manufacturing them 有权
    高K介电材料及其制造方法

    公开(公告)号：US07732852B2

    公开(公告)日：2010-06-08

    申请号：US11499308

    申请日：2006-08-03

    申请人： Jiong-Ping Lu ,  Ming-Jang Hwang

    发明人： Jiong-Ping Lu ,  Ming-Jang Hwang

    IPC分类号： H01L27/108

    CPC分类号： C23C16/34 ,  C23C16/56 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31683 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/57

    摘要： High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition (CVD) of the respective nitrides and annealing in the presence of oxygen to densify and oxidize the nitrides. The resulting film is useful as a capacitative cell and resists oxygen diffusion to the underlying material, has high capacitance and low current leakage.

    摘要翻译： 通过相应氮化物的顺序化学气相沉积（CVD）形成钛和钨或钛和钽的混合过渡金属氧化物的高介电膜，并在氧的存在下退火以致密化和氧化氮化物。 所得到的膜可用作电容性电池并且抵抗向下层材料的氧扩散，具有高电容和低电流泄漏。

    Process method to facilitate silicidation
    6.
    发明授权
    Process method to facilitate silicidation 有权
    硅化方法

    公开(公告)号：US07448395B2

    公开(公告)日：2008-11-11

    申请号：US10894374

    申请日：2004-07-19

    申请人： Jiong-Ping Lu ,  Freidoon Mehrad ,  Lindsey Hall ,  Vivian Liu ,  Clint Montgomery ,  Scott Johnson

    发明人： Jiong-Ping Lu ,  Freidoon Mehrad ,  Lindsey Hall ,  Vivian Liu ,  Clint Montgomery ,  Scott Johnson

    IPC分类号： B08B6/00 ,  C25F1/00 ,  C25F3/30 ,  C25F5/00

    CPC分类号： H01L21/28518 ,  H01L21/02046 ,  H01L21/0206 ,  H01L21/28052 ,  H01L29/665

    摘要： The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.

    摘要翻译： 本发明在将钴层124沉积在硅衬底和/或多晶硅材料上之前基本上从干等离子体蚀刻工艺110去除干蚀刻残留物。 随后，进行一个或多个退火工艺128，其使钴与硅反应，从而形成硅化钴区域。 残留在沉积的钴和下面的硅之间的干蚀刻残留物的缺乏允许用期望的硅化物片和接触电阻基本上均匀地形成硅化钴区域。 通过执行第一清洁操作112，然后进行包括合适的清洁溶液的延长清洁操作114，基本上去除了干蚀刻残留物。 第一次清洁操作通常去除一些但不是全部的干蚀刻残留物。 延长的清洁操作114在更高的温度和/或延长的持续时间内进行，并且基本上去除了在第一清洁操作112之后残留的干蚀刻残留物。

    Method for manufacturing a semiconductor device having silicided regions
    7.
    发明授权
    Method for manufacturing a semiconductor device having silicided regions 有权
    制造具有硅化物区域的半导体器件的方法

    公开(公告)号：US07422968B2

    公开(公告)日：2008-09-09

    申请号：US10901756

    申请日：2004-07-29

    申请人： Jiong-Ping Lu ,  Clint Montgomery ,  Lindsey Hall ,  Donald Miles ,  Duofeng Yue ,  Thomas D. Bonifiield

    发明人： Jiong-Ping Lu ,  Clint Montgomery ,  Lindsey Hall ,  Donald Miles ,  Duofeng Yue ,  Thomas D. Bonifiield

    IPC分类号： H01L21/425

    CPC分类号： H01L21/823835 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/02068 ,  H01L27/0629 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device (100) , among other steps, includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes subjecting the gate structure (120) and substrate (110) to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains (320) subsequent to subjecting the gate structure (120) and substrate (110) to the dry etch process. Thereafter, the method includes forming metal silicide regions (510, 520) in the gate structure (120) and the fluorinated source/drains (320).

    摘要翻译： 本发明提供一种半导体器件的制造方法以及包括该半导体器件的集成电路的制造方法。 除了其他步骤之外，用于制造半导体器件（100）的方法包括在衬底（110）上形成栅极结构（120）并且在栅极结构（120）附近的衬底（110）中形成源极/漏极区域（190） ）。 该方法还包括对栅极结构（120）和衬底（110）进行干蚀刻工艺，并且在将栅极结构（120）和衬底（120）经受栅极结构（120）和衬底 （110）到干蚀刻工艺。 此后，该方法包括在栅极结构（120）和氟化源极/漏极（320）中形成金属硅化物区域（510,520）。

    Process method to optimize fully silicided gate (FUSI) thru PAI implant
    8.
    发明申请
    Process method to optimize fully silicided gate (FUSI) thru PAI implant 审中-公开
    通过PAI植入物优化完全硅化栅（FUSI）的工艺方法

    公开(公告)号：US20080206973A1

    公开(公告)日：2008-08-28

    申请号：US11710769

    申请日：2007-02-26

    申请人： Frank Scott Johnson ,  Freidoon Mehrad ,  Jiong-Ping Lu

    发明人： Frank Scott Johnson ,  Freidoon Mehrad ,  Jiong-Ping Lu

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/26506 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

    摘要： An improved method of forming a fully silicided (FUSI) gate in both NMOS and PMOS transistors of the same MOS device is disclosed. In one example, the method comprises forming oxide and nitride etch-stop layers over a top portion of the gates of the NMOS and PMOS transistors, forming a blocking layer over the etch-stop layer, planarizing the blocking layer down to the etch-stop layer over the gates, and removing a portion of the etch-stop layer overlying the gates. The method further includes implanting a preamorphizing species into the exposed gates to amorphize the gates, thereby permitting uniform silicide formation thereafter at substantially the same rates in the NMOS and PMOS transistors. The method may further comprise removing any remaining oxide or blocking layers, forming the gate silicide over the gates to form the FUSI gates, and forming source/drain silicide in moat areas of the NMOS and PMOS transistors.

    摘要翻译： 公开了在相同MOS器件的NMOS和PMOS晶体管中形成完全硅化（FUSI）栅极的改进方法。 在一个示例中，该方法包括在NMOS和PMOS晶体管的栅极的顶部部分上形成氧化物和氮化物蚀刻停止层，在蚀刻停止层上形成阻挡层，将阻挡层平坦化到蚀刻停止 并且去除覆盖在栅极上的蚀刻停止层的一部分。 该方法还包括将预变质物质注入到暴露的栅极中以使栅极非晶化，从而在NMOS和PMOS晶体管中以基本上相同的速率允许均匀的硅化物形成。 该方法还可以包括去除任何剩余的氧化物或阻挡层，在栅极上形成栅极硅化物以形成FUSI栅极，以及在NMOS和PMOS晶体管的护环区域中形成源极/漏极硅化物。

    Formation of a Selective Carbon-Doped Epitaxial Cap Layer on Selective Epitaxial SiGe
    9.
    发明申请
    Formation of a Selective Carbon-Doped Epitaxial Cap Layer on Selective Epitaxial SiGe 有权
    在选择性外延SiGe上形成选择性碳掺杂外延帽盖层

    公开(公告)号：US20080199999A1

    公开(公告)日：2008-08-21

    申请号：US11677496

    申请日：2007-02-21

    申请人： Johan Weijtmans ,  Jiong-Ping Lu ,  Rick Wise

    发明人： Johan Weijtmans ,  Jiong-Ping Lu ,  Rick Wise

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7834 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method for forming epitaxial SiGe of a PMOS transistor. In an example embodiment, the method may include providing a semiconductor wafer having a PMOS transistor gate stack, extension sidewalls, source/drain extension regions, and active regions. The method may also include performing a recess etch of the active regions and forming epitaxial SiGe within the recessed active regions by forming a selective epi SiGe region coupled to the surface of the recessed active regions and a selective carbon-doped epitaxial cap layer coupled to the selective epi SiGe region.

    摘要翻译： 一种用于形成PMOS晶体管的外延SiGe的方法。 在示例实施例中，该方法可以包括提供具有PMOS晶体管栅极堆叠，延伸侧壁，源极/漏极延伸区域和有源区域的半导体晶片。 该方法还可以包括通过形成耦合到凹入的有源区域的表面的选择性外延SiGe区域和耦合到凹陷的有源区域的选择性碳掺杂的外延盖层，来执行有源区域的凹陷蚀刻并在凹入的有源区域内形成外延SiGe 选择性epi SiGe区域。