公开(公告)号：US06359339B1

公开(公告)日：2002-03-19

申请号：US09480224

申请日：2000-01-10

申请人： Richard W. Gregor ,  Isik C. Kizilyalli ,  Sailesh M. Merchant ,  Jaseph R. Radosevich ,  Pradip K. Roy

发明人： Richard W. Gregor ,  Isik C. Kizilyalli ,  Sailesh M. Merchant ,  Jaseph R. Radosevich ,  Pradip K. Roy

IPC分类号： H01L2348

CPC分类号： H01L28/24 ,  H01L27/0802

摘要： The present invention provides a unique a resistor formed on a semiconductor substrate. The resistor preferably comprises a first resistor layer that includes a first metal silicide, such as tungsten silicide, and nitrogen and that is formed on the substrate. The first layer has a first thickness and a concentration of nitrogen incorporated therein. The nitrogen concentration may be varied to obtain a desired resistive value of the resistor. Thus, depending on the concentration of nitrogen, a wide range of resistive values may be achieved. The resistor further comprises a second resistor layer with a second thickness that includes a second metal silicide and that is formed on the first resistor layer. Thus, the present invention provides a metal silicide-based resistor having nitrogen incorporated therein which allows the resistance of the resistor to be tailored to specific electrical applications. Yet at the same time, the resistor is far less susceptible to temperature and voltage variation than conventional diffused resistors and, thereby, provides a more precise resistor.

摘要翻译： 本发明提供了形成在半导体衬底上的独特的电阻器。 电阻器优选地包括第一电阻层，该第一电阻层包括第一金属硅化物，例如硅化钨和氮，并且形成在衬底上。 第一层具有掺入其中的第一厚度和氮浓度。 可以改变氮浓度以获得电阻器的期望电阻值。 因此，取决于氮的浓度，可以实现宽范围的电阻值。 电阻器还包括具有第二厚度的第二电阻层，该第二电阻层包括第二金属硅化物，并形成在第一电阻层上。 因此，本发明提供一种其中结合有氮化物的金属硅化物基电阻器，其允许将电阻器的电阻定制为特定的电气应用。 然而与此同时，电阻器比常规扩散电阻器更不易受温度和电压变化的影响，从而提供更精确的电阻器。

公开(公告)号：US6090686A

公开(公告)日：2000-07-18

申请号：US878242

申请日：1997-06-18

申请人： David C. Brady ,  Isik C. Kizilyalli ,  Pradip K. Roy ,  Hem M. Vaidya

发明人： David C. Brady ,  Isik C. Kizilyalli ,  Pradip K. Roy ,  Hem M. Vaidya

IPC分类号： H01L21/316 ,  H01L21/318 ,  H01L21/32 ,  H01L21/76

CPC分类号： H01L21/3185 ,  H01L21/32

摘要： The present invention provides methods of manufacturing a field oxide isolation structure over a semiconductor. One of the methods includes the steps of: (1) depositing a first stack-nitride sublayer over the semiconductor at a first deposition rate and (2) subsequently depositing a second stack-nitride sublayer over the first stack-sublayer at a second deposition rate that is either greater or less than the first deposition rate. The first and second deposition rates provide first and second stack-nitride sublayers that cooperate to form a relatively thin, uniform thickness of the field oxide isolation structure over the semiconductor and provide a stress-accommodating system within the semiconductor. The varying rates of deposition and accompanying changes in mixture ratio, produce a stack that is better able to absorb stress, has greater uniformity and is far less subject to the disadvantageous phenomenon of stack-lifting, particularly encountered in semiconductor having a PADOX layer deposited thereon.

公开(公告)号：US06281138B1

公开(公告)日：2001-08-28

申请号：US09338939

申请日：1999-06-24

申请人： David C. Brady ,  Isik C. Kizilyalli ,  Yi Ma ,  Pradip K. Roy

发明人： David C. Brady ,  Isik C. Kizilyalli ,  Yi Ma ,  Pradip K. Roy

IPC分类号： H01L2131

CPC分类号： H01L21/28185 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02208 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31612 ,  H01L29/513 ,  H01L29/518

摘要： This invention includes a novel synthesis of a three-step process of growing, depositing and growing SiO2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer, which contains a substantial concentration of a hydrogen isotope, such as deuterium, forms an interface with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated SiO2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps.

摘要翻译： 本发明包括在低压例如0.2-10乇下生长，沉积和生长SiO 2的三步法的新型合成，以产生用于亚0.5微米技术的高质量，坚固和可靠的栅极氧化物。 对第一层，1.0-3.0nm进行热生长以钝化Si半导体表面。 包含相当浓度的氢同位素（例如氘）的第二沉积层与第一生长层形成界面。 在沉积的氧化物层的合成致密化的第三步骤中，同时去除界面处的界面陷阱并且在存在应力容纳的情况下在Si /第一生长层界面处发生应力调制的SiO 2的生长 界面层，产生平面和应力降低的Si / SiO 2界面。 整个合成在低压（例如，0.2-10托）下进行，以减缓氧化动力学以达到超薄亚层，并且可以通过聚集所有三个步骤在单个低压炉中进行。

公开(公告)号：US06380606B1

公开(公告)日：2002-04-30

申请号：US09205413

申请日：1998-12-02

申请人： David C. Brady ,  Isik C. Kizilyalli ,  Pradip K. Roy ,  Hem M. Vaidya

发明人： David C. Brady ,  Isik C. Kizilyalli ,  Pradip K. Roy ,  Hem M. Vaidya

IPC分类号： H01L2900

CPC分类号： H01L21/3185 ,  H01L21/32

摘要： The present invention provides methods of manufacturing a field oxide isolation structure over a semiconductor. One of the methods includes the steps of: (1) depositing a first stack-nitride sublayer over the semiconductor at a first deposition rate and (2) subsequently depositing a second stack-nitride sublayer over the first stack-sublayer at a second deposition rate that is either greater or less than the first deposition rate. The first and second deposition rates provide first and second stack-nitride sublayers that cooperate to form a relatively thin, uniform thickness of the field oxide isolation structure over the semiconductor and provide a stress-accommodating system within the semiconductor. The varying rates of deposition and accompanying changes in mixture ratio, produce a stack that is better able to absorb stress, has greater uniformity and is far less subject to the disadvantageous phenomenon of stack-lifting, particularly encountered in semiconductor having a PADOX layer deposited thereon.

摘要翻译： 本发明提供在半导体上制造场氧化物隔离结构的方法。 其中一种方法包括以下步骤：（1）以第一沉积速率在半导体上沉积第一堆叠氮化物子层，以及（2）随后以第二沉积速率在第一堆叠子层上沉积第二堆叠氮化物层 大于或小于第一沉积速率。 第一和第二沉积速率提供第一和第二堆叠氮化物层，其协作以在半导体上形成场氧化物隔离结构的相对薄的均匀厚度，并在半导体内提供应力容纳系统。 不同的沉积速率和伴随的混合比例的变化产生更好地吸收应力的叠层，具有更大的均匀性，并且远远少于堆叠提升的不利现象，特别是在其上沉积有PADOX层的半导体中遇到 。

公开(公告)号：US6025280A

公开(公告)日：2000-02-15

申请号：US848109

申请日：1997-04-28

申请人： David C. Brady ,  Isik C. Kizilyalli ,  Yi Ma ,  Pradip K. Roy

发明人： David C. Brady ,  Isik C. Kizilyalli ,  Yi Ma ,  Pradip K. Roy

IPC分类号： C23C16/40 ,  H01L21/28 ,  H01L21/316 ,  H01L29/51

CPC分类号： H01L21/28185 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02208 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31612 ,  H01L29/513 ,  H01L29/518

摘要： This invention includes a novel synthesis of a three-step process of growing, depositing and growing SiO.sub.2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer, which contains a substantial concentration of a hydrogen isotope, such as deuterium, forms an interface with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated SiO.sub.2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO.sub.2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps. For light nitrogen-incorporation (

摘要翻译： 本发明包括在低压例如0.2-10乇下生长，沉积和生长SiO 2的三步法的新型合成，以产生用于亚0.5微米技术的高质量，坚固和可靠的栅极氧化物。 对第一层，1.0-3.0nm进行热生长以钝化Si半导体表面。 包含相当浓度的氢同位素（例如氘）的第二沉积层与第一生长层形成界面。 在沉积的氧化物层的合成致密化的第三步骤中，同时去除界面处的界面陷阱并且在应力容纳的存在下在Si /第一生长层界面处发生应力调制的SiO 2的生长 界面层，产生平面和应力降低的Si / SiO 2界面。 整个合成在低压（例如，0.2-10托）下进行，以减缓氧化动力学以达到超薄亚层，并且可以通过聚集所有三个步骤在单个低压炉中进行。 对于某些器件的轻氮掺入（<5％），通常由于提高的耐硼性和其他掺杂剂扩散性和热载流子特性而需要，因此在层叠氧化物合成的每个步骤期间都使用氧化剂中的N2O或NO。 平面和应力降低的Si / SiO 2界面特性是层叠氧化物的独特标志，其改善了栅极氧化物对ULSI处理的鲁棒性，导致器件参数（例如，阈值电压，跨导），迁移率降低和耐热性降低的散射 载体和福勒 - 诺德海姆压力。

公开(公告)号：US06313021B1

公开(公告)日：2001-11-06

申请号：US09416491

申请日：1999-10-12

申请人： Sailesh M. Merchant ,  Joseph R. Radosevich ,  Pradip K. Roy

发明人： Sailesh M. Merchant ,  Joseph R. Radosevich ,  Pradip K. Roy

IPC分类号： H01L213205

CPC分类号： H01L21/28035 ,  H01L21/28044 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4933 ,  H01L29/4941

摘要： The present invention provides a process for forming a sub-micron p-type metal oxide semiconductor (PMOS) structure on a semiconductor substrate. The process includes forming a gate oxide on the semiconductor substrate, forming a gate layer on the gate oxide by depositing a first gate layer on the gate oxide at a first deposition rate and depositing a second gate layer on the first layer at a second deposition rate to provide an improved stress accommodation within the gate structure. The process further includes forming a silicide dopant barrier on the gate. Due to the presence of the improved stress accommodation in the gate, the integrity of the silicide dopant barrier is substantially enhanced. This increased silicide integrity prevents significant damage to the silicide dopant barrier layer during subsequent fabrication processes. As such, the dopant barrier is able to provide the intended degree of resistance to dopant penetration, for example boron, during the formation of source and drain regions adjacent the gate structure.

摘要翻译： 本发明提供了一种在半导体衬底上形成亚微米p型金属氧化物半导体（PMOS）结构的方法。 该工艺包括在半导体衬底上形成栅极氧化物，通过以第一沉积速率沉积栅极氧化物上的第一栅极层，以栅极氧化物形成栅极层，并以第二沉积速率在第一层上沉积第二栅极层 以在门结构内提供改进的应力调节。 该工艺还包括在栅极上形成硅化物掺杂剂阻挡层。 由于在栅极中存在改善的应力调节，硅化物掺杂剂势垒的完整性显着增强。 这种增加的硅化物完整性防止在随后的制造工艺期间对硅化物掺杂剂阻挡层的显着损坏。 因此，在形成与栅极结构相邻的源极和漏极区域期间，掺杂物势垒能够提供对掺杂剂穿透（例如硼）的预期程度的阻抗。

公开(公告)号：US5523259A

公开(公告)日：1996-06-04

申请号：US349649

申请日：1994-12-05

申请人： Sailesh M. Merchant ,  Arun K. Nanda ,  Pradip K. Roy

发明人： Sailesh M. Merchant ,  Arun K. Nanda ,  Pradip K. Roy

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/5329 ,  H01L23/5226 ,  H01L2924/0002

摘要： In an integrated circuit, an opening (e.g., via or window) is filled with an Al-based plug which has essentially a orientation and comprises at most three grains. These characteristics are achieved by first depositing a texture control Ti layer having substantially a (002) basal plane orientation followed by at least three Al-based sublayers. The grain sizes and deposition conditions are controlled in such a way that during deposition of the third sublayer, the microstructure of the plug adjusts itself to produce a single grain (or at most three).

摘要翻译： 在集成电路中，开口（例如，通孔或窗口）填充有基本上为111°取向且至多包含三个晶粒的Al-基塞。 这些特性通过首先沉积具有基本上（002）基面平面取向的纹理控制Ti层，然后是至少三个基于Al的子层来实现。 晶粒尺寸和沉积条件被控制为在沉积第三子层期间，插塞的微观结构自身调整以产生单个颗粒（或至多三个）。

公开(公告)号：US06323078B1

公开(公告)日：2001-11-27

申请号：US09418106

申请日：1999-10-14

申请人： Siddhartha Bhowmik ,  Sailesh M. Merchant ,  Pradip K. Roy ,  Sidhartha Sen

发明人： Siddhartha Bhowmik ,  Sailesh M. Merchant ,  Pradip K. Roy ,  Sidhartha Sen

IPC分类号： H01L218234

CPC分类号： H01L28/40

摘要： The present invention provides a method of forming a metal oxide metal (MOM) capacitor on a substrate, such as a silicon substrate, of a semiconductor wafer in a rapid thermal process (RTP) machine. The MOM capacitor is fabricated by forming a metal layer on the semiconductor substrate. The metal layer is then subjected to a first rapid thermal process in a substantially inert but nitrogen-free atmosphere that consumes a portion of the metal layer to form a first metal electrode layer and a silicide layer between the first metal electrode and the semiconductor substrate. The semiconductor wafer is then subjected to a second rapid thermal process. During this process, the remaining portion of the metal layer is oxidized to form a metal oxide on the first metal electrode, which serves as the dielectric layer of the MOM capacitor. Following the formation of the dielectric layer, a second metal electrode layer is then conventionally formed on the metal oxide, which completes the formation of the MOM capacitor. Preferably, the first electrode layer and the metal oxide layer are formed in a single RTP machine.

摘要翻译： 本发明提供了一种在快速热处理（RTP）机器中在半导体晶片的衬底（例如硅衬底）上形成金属氧化物金属（MOM）电容器的方法。 通过在半导体衬底上形成金属层来制造MOM电容器。 然后在基本惰性但无氮的气氛中对金属层进行第一快速热处理，其消耗金属层的一部分以在第一金属电极和半导体衬底之间形成第一金属电极层和硅化物层。 然后对半导体晶片进行第二快速热处理。 在该过程中，金属层的剩余部分被氧化，在作为MOM电容器的电介质层的第一金属电极上形成金属氧化物。 在形成电介质层之后，通常在金属氧化物上形成第二金属电极层，从而完成MOM电容器的形成。 优选地，第一电极层和金属氧化物层在单个RTP机器中形成。

公开(公告)号：US5489552A

公开(公告)日：1996-02-06

申请号：US366529

申请日：1994-12-30

申请人： Sailesh M. Merchant ,  Arun K. Nanda ,  Pradip K. Roy

发明人： Sailesh M. Merchant ,  Arun K. Nanda ,  Pradip K. Roy

IPC分类号： C23C4/06 ,  C23C26/00 ,  H01L21/203 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/44 ,  H01L21/443

CPC分类号： H01L21/76838 ,  H01L21/28556

摘要： Tungsten plugs are formed in a manner which avoids the formation of unwanted tungsten volcanoes by depositing at least three and preferably five to seven layers of tungsten within a contact hole to form a layered plug. In particularly useful embodiments, the layers are deposited at alternating fast and slow rates of deposition.

摘要翻译： 通过在接触孔内沉积至少三个，优选五至七层的钨以形成分层塞，避免形成不需要的钨火山的钨塞。 在特别有用的实施方案中，以交替的快速和慢速沉积速率沉积这些层。

公开(公告)号：US6153452A

公开(公告)日：2000-11-28

申请号：US782010

申请日：1997-01-07

申请人： Sailesh M. Merchant ,  Arun K. Nanda ,  Pradip K. Roy ,  Hem M. Vaidya

发明人： Sailesh M. Merchant ,  Arun K. Nanda ,  Pradip K. Roy ,  Hem M. Vaidya

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49

CPC分类号： H01L21/28061 ,  H01L21/823835 ,  H01L29/4933

摘要： Methods of manufacturing a semiconductor device. One method includes the steps of: (1) providing a substrate over which is to be deposited a metal silicide layer having a stoichiometric ratio within a desired range, (2) providing a target composed of a metal silicide, the target subject to degradation by reason of use, (3) sputtering atoms from the target to form the metal silicide layer over the substrate, the stoichiometric ratio subject to being without the desired range by reason of the degradation of the target and (4) depositing a predetermined amount of silicon on the metal silicide layer to return the stoichiometric ratio to within the desired range, a useful life of the target thereby increased.

摘要翻译： 制造半导体器件的方法。 一种方法包括以下步骤：（1）提供要在其上沉积化学计量比在所需范围内的金属硅化物层的衬底，（2）提供由金属硅化物组成的靶，靶由 使用原因，（3）从靶上溅射原子以在衬底上形成金属硅化物层，化学计量比由于靶的劣化而不具有所需的范围，（4）沉积预定量的硅 在金属硅化物层上以将化学计量比返回到所需范围内，从而靶的使用寿命增加。