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    Platinum ohmic contact to p-type silicon carbide
    1.
    发明授权
    Platinum ohmic contact to p-type silicon carbide 失效
    铂欧姆接触到p型碳化硅

    公开(公告)号：US5323022A

    公开(公告)日：1994-06-21

    申请号：US943043

    申请日：1992-09-10

    申请人： Robert C. Glass ,  John W. Palmour ,  Robert F. Davis ,  Lisa S. Porter

    发明人： Robert C. Glass ,  John W. Palmour ,  Robert F. Davis ,  Lisa S. Porter

    IPC分类号： H01L29/43 ,  H01L21/04 ,  H01L21/28 ,  H01L29/24 ,  H01L29/45 ,  H01L29/40 ,  H01L29/46 ,  H01L29/62

    CPC分类号： H01L29/1608 ,  H01L21/0485 ,  H01L29/45 ,  Y10S148/148

    摘要： A method and resulting ohmic contact structure between a high work function metal and a wide bandgap semiconductor for which the work function of the metal would ordinarily be insufficient to form an ohmic contact between the metal and the semiconductor. The structure can withstand annealing while retaining ohmic characteristics. The ohmic contact structure comprises a portion of single crystal wide bandgap semiconductor material; a contact formed of a high work function metal on the semiconductor portion; and a layer of doped p-type semiconductor material between the single crystal portion and the metal contact. The doped layer has a sufficient concentration of p-type dopant to provide ohmic behavior between the metal and the semiconductor material.

    摘要翻译： 高功函数金属和宽带隙半导体之间的方法和结果欧姆接触结构，金属的功函数通常不足以在金属和半导体之间形成欧姆接触。 该结构可以承受退火同时保持欧姆特性。 欧姆接触结构包括单晶宽带隙半导体材料的一部分; 在半导体部分上由高功函数金属形成的触点; 以及在单晶部分和金属接触之间的掺杂p型半导体材料层。 掺杂层具有足够的p型掺杂剂浓度以在金属和半导体材料之间提供欧姆特性。

    Method of forming platinum ohmic contact to p-type silicon carbide
    2.
    发明授权
    Method of forming platinum ohmic contact to p-type silicon carbide 失效
    用于形成与p型碳化硅的铂欧姆接触的方法

    公开(公告)号：US5409859A

    公开(公告)日：1995-04-25

    申请号：US231389

    申请日：1994-04-22

    申请人： Robert C. Glass ,  John W. Palmour ,  Robert F. Davis ,  Lisa S. Porter

    发明人： Robert C. Glass ,  John W. Palmour ,  Robert F. Davis ,  Lisa S. Porter

    IPC分类号： H01L29/43 ,  H01L21/04 ,  H01L21/28 ,  H01L29/24 ,  H01L29/45 ,  H01L21/283

    CPC分类号： H01L29/1608 ,  H01L21/0485 ,  H01L29/45 ,  Y10S148/148

    摘要： A method and resulting ohmic contact structure between a high work function metal and a wide bandgap semiconductor for which the work function of the metal would ordinarily be insufficient to form an ohmic contact between the metal and the semiconductor. The structure can withstand annealing while retaining ohmic characteristics. The ohmic contact structure comprises a portion of single crystal wide bandgap semiconductor material; a contact formed of a high work function metal on the semiconductor portion; and a layer of doped p-type semiconductor material between the single crystal portion and the metal contact. The doped layer has a sufficient concentration of p-type dopant to provide ohmic behavior between the metal and the semiconductor material.

    摘要翻译： 高功函数金属和宽带隙半导体之间的方法和结果欧姆接触结构，金属的功函数通常不足以在金属和半导体之间形成欧姆接触。 该结构可以承受退火同时保持欧姆特性。 欧姆接触结构包括单晶宽带隙半导体材料的一部分; 在半导体部分上由高功函数金属形成的触点; 以及在单晶部分和金属接触之间的掺杂p型半导体材料层。 掺杂层具有足够的p型掺杂剂浓度以在金属和半导体材料之间提供欧姆特性。

    Methods of forming zinc oxide based II-VI compound semiconductor layers with shallow acceptor conductivities
    5.
    发明授权
    Methods of forming zinc oxide based II-VI compound semiconductor layers with shallow acceptor conductivities 失效
    形成具有浅受主电导率的氧化锌基II-VI化合物半导体层的方法

    公开(公告)号：US07723154B1

    公开(公告)日：2010-05-25

    申请号：US11551058

    申请日：2006-10-19

    申请人： Bunmi T. Adekore ,  Jonathan M. Pierce ,  Robert F. Davis ,  George B. Kenney

    发明人： Bunmi T. Adekore ,  Jonathan M. Pierce ,  Robert F. Davis ,  George B. Kenney

    IPC分类号： H01L21/00

    CPC分类号： H01L21/02565 ,  H01L21/0237 ,  H01L21/02554 ,  H01L21/02573 ,  H01L21/02579 ,  H01L21/02581 ,  H01L21/0262 ,  H01L21/425

    摘要： A p-type ZnO-based II-VI compound semiconductor layer has silver, potassium and/or gold dopants therein at a net p-type dopant concentration of greater than about 1×1017 cm−3. A method of forming the layer includes using an atomic layer deposition (ALD) technique. This technique includes exposing a substrate to a combination of gases: a first reaction gas containing zinc at a concentration that is repeatedly transitioned between at least two concentration levels during a processing time interval, a second reaction gas containing oxygen and a p-type dopant gas containing at least one p-type dopant species selected from a group consisting of silver, potassium and gold. A concentration of oxygen in the second reaction gas may also be repeatedly transitioned between at least two concentration levels. The concentration of zinc in the first reaction gas and the concentration of oxygen in the second reaction gas may be transitioned in an alternating sequence, so that relatively high zinc concentrations in the first reaction gas overlap with relatively low oxygen concentrations in the second reaction gas and vice versa.

    摘要翻译： p型ZnO基II-VI化合物半导体层在其中具有大于约1×1017cm-3的净p型掺杂剂浓度的银，钾和/或金掺杂剂。 形成层的方法包括使用原子层沉积（ALD）技术。 这种技术包括将基底暴露于气体组合中：在处理时间间隔内以至少两个浓度水平重复过渡浓度的锌的第一反应气体，含有氧的第二反应气体和p型掺杂气体 含有选自银，钾和金的至少一种p型掺杂剂物质。 第二反应气体中的氧浓度也可以在至少两个浓度水平之间重复地转变。 第一反应气体中的锌的浓度和第二反应气体中的氧浓度可以以交替的顺序转变，使得第一反应气体中相对较高的锌浓度与第二反应气体中相对较低的氧浓度重叠， 反之亦然。

    Gallium nitride semiconductor structure including laterally offset patterned layers
    6.
    发明授权
    Gallium nitride semiconductor structure including laterally offset patterned layers 失效
    包括横向偏移的图案化层的氮化镓半导体结构

    公开(公告)号：US06608327B1

    公开(公告)日：2003-08-19

    申请号：US09031843

    申请日：1998-02-27

    申请人： Robert F. Davis ,  Ok-Hyun Nam

    发明人： Robert F. Davis ,  Ok-Hyun Nam

    IPC分类号： H01L310256

    CPC分类号： H01L21/0262 ,  H01L21/0237 ,  H01L21/02378 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007

    摘要： A gallium nitride semiconductor layer is fabricated by masking an underlying gallium nitride layer with a first mask that includes a first array of openings therein and growing the underlying gallium nitride layer through the first array of openings and onto the first mask, to thereby form a first overgrown gallium nitride semiconductor layer. The first overgrown layer is then masked with the second mask that includes a second array of openings therein. The second array of openings is laterally offset from the first array of openings. The first overgrown gallium nitride layer is then grown through the second array of openings and onto the second mask, to thereby form a second overgrown gallium nitride semiconductor layer. Microelectronic devices may then be formed in the second overgrown gallium nitride semiconductor layer.

    摘要翻译： 通过用包括第一阵列开口的第一掩模掩蔽下面的氮化镓层来制造氮化镓半导体层，并通过第一开口阵列生长下面的氮化镓层，并且形成第一掩模 杂草生长的氮化镓半导体层。 然后用包括其中的第二开口阵列的第二掩模掩蔽第一长满的层。 第二阵列的开口横向偏离第一阵列的开口。 然后通过第二阵列的开口将第一长满的氮化镓层生长到第二掩模上，从而形成第二长满的氮化镓半导体层。 然后可以在第二长满的氮化镓半导体层中形成微电子器件。

    Pendeoepitaxial gallium nitride semiconductor layers on silicon carbide substrates
    7.
    发明授权
    Pendeoepitaxial gallium nitride semiconductor layers on silicon carbide substrates 有权

    公开(公告)号：US06462355B1

    公开(公告)日：2002-10-08

    申请号：US09717717

    申请日：2000-11-21

    申请人： Kevin J. Linthicum ,  Thomas Gehrke ,  Darren B. Thomson ,  Eric P. Carlson ,  Pradeep Rajagopal ,  Robert F. Davis

    发明人： Kevin J. Linthicum ,  Thomas Gehrke ,  Darren B. Thomson ,  Eric P. Carlson ,  Pradeep Rajagopal ,  Robert F. Davis

    IPC分类号： H01L29267

    CPC分类号： C30B25/02 ,  C30B29/406 ,  H01L21/02378 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265

    摘要： An underlying gallium nitride layer on a silicon carbide substrate is masked with a mask that includes an array of openings therein, and the underlying gallium nitride layer is etched through the array of openings to define posts in the underlying gallium nitride layer and trenches therebetween. The posts each include a sidewall and a top having the mask thereon. The sidewalls of the posts are laterally grown into the trenches to thereby form a gallium nitride semiconductor layer. During this lateral growth, the mask prevents nucleation and vertical growth from the tops of the posts. Accordingly, growth proceeds laterally into the trenches, suspended from the sidewalls of the posts. The sidewalls of the posts may be laterally grown into the trenches until the laterally grown sidewalls coalesce in the trenches to thereby form a gallium nitride semiconductor layer. The lateral growth from the sidewalls of the posts may be continued so that the gallium nitride layer grows vertically through the openings in the mask and laterally overgrows onto the mask on the tops of the posts, to thereby form a gallium nitride semiconductor layer. The lateral overgrowth can be continued until the grown sidewalls coalesce on the mask to thereby form a continuous gallium nitride semiconductor layer. Microelectronic devices may be formed in the continuous gallium nitride semiconductor layer.

    PENDEOEPITAXIAL METHODS OF FABRICATING GALLIUM NITRIDE SEMICONDUCTOR LAYERS ON SILICON CARBIDE SUBSTRATES BY LATERAL GROWTH FROM SIDEWALLS OF MASKED POSTS, AND GALLIUM NITRIDE SEMICONDUCTOR STRUCTURES FABRICATED THEREBY
    8.
    发明授权
    PENDEOEPITAXIAL METHODS OF FABRICATING GALLIUM NITRIDE SEMICONDUCTOR LAYERS ON SILICON CARBIDE SUBSTRATES BY LATERAL GROWTH FROM SIDEWALLS OF MASKED POSTS, AND GALLIUM NITRIDE SEMICONDUCTOR STRUCTURES FABRICATED THEREBY 有权
    通过边缘生长形成的硅碳化物基板上的氮化钛半导体层的制备方法和氮化钛半导体结构的制备方法

    公开(公告)号：US06376339B2

    公开(公告)日：2002-04-23

    申请号：US09780072

    申请日：2001-02-09

    申请人： Kevin J. Linthicum ,  Thomas Gehrke ,  Darren B. Thomson ,  Eric P. Carlson ,  Pradeep Rajagopal ,  Robert F. Davis

    发明人： Kevin J. Linthicum ,  Thomas Gehrke ,  Darren B. Thomson ,  Eric P. Carlson ,  Pradeep Rajagopal ,  Robert F. Davis

    IPC分类号： H01L2120

    CPC分类号： C30B25/02 ,  C30B29/406 ,  H01L21/02378 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265

    摘要： An underlying gallium nitride layer on a silicon carbide substrate is masked with a mask that includes an array of openings therein, and the underlying gallium nitride layer is etched through the array of openings to define posts in the underlying gallium nitride layer and trenches therebetween. The posts each include a sidewall and a top having the mask thereon. The sidewalls of the posts are laterally grown into the trenches to thereby form a gallium nitride semiconductor layer. During this lateral growth, the mask prevents nucleation and vertical growth from the tops of the posts. Accordingly, growth proceeds laterally into the trenches, suspended from the sidewalls of the posts. The sidewalls of the posts may be laterally grown into the trenches until the laterally grown sidewalls coalesce in the trenches to thereby form a gallium nitride semiconductor layer. The lateral growth from the sidewalls of the posts may be continued so that the gallium nitride layer grows vertically through the openings in the mask and laterally overgrows onto the mask on the tops of the posts, to thereby form a gallium nitride semiconductor layer. The lateral overgrowth can be continued until the grown sidewalls coalesce on the mask to thereby form a continuous gallium nitride semiconductor layer. Microelectronic devices may be formed in the continuous gallium nitride semiconductor layer.

    摘要翻译： 在碳化硅衬底上的下面的氮化镓层用掩模进行掩模，该掩模包括其中的开口阵列，并且通过开口阵列蚀刻下面的氮化镓层，以在下面的氮化镓层和沟槽之间形成沟槽。 所述柱各自包括侧壁和其上具有掩模的顶部。 柱的侧壁横向生长到沟槽中，从而形成氮化镓半导体层。 在这种侧向生长期间，面罩防止从柱的顶部成核和垂直生长。 因此，生长横向进入沟槽，从柱的侧壁悬挂。 柱的侧壁可以横向生长到沟槽中，直到横向生长的侧壁在沟槽中聚结，从而形成氮化镓半导体层。 可以继续从柱的侧壁的横向生长，使得氮化镓层垂直地通过掩模中的开口生长，并且横向过度地延伸到柱的顶部上的掩模上，从而形成氮化镓半导体层。 横向过度生长可以继续，直到生长的侧壁在掩模上聚结，从而形成连续的氮化镓半导体层。 微电子器件可以形成在连续的氮化镓半导体层中。