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    Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature
    1.
    发明授权
    Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature 失效
    容错计算机存储器系统和采用双级错误校正和检测功能的组件

    公开(公告)号：US5682394A

    公开(公告)日：1997-10-28

    申请号：US012186

    申请日：1993-02-02

    申请人： Robert Martin Blake ,  Douglas Craig Bossen ,  Chin-Long Chen ,  John Atkinson Fifield ,  Howard Leo Kalter

    发明人： Robert Martin Blake ,  Douglas Craig Bossen ,  Chin-Long Chen ,  John Atkinson Fifield ,  Howard Leo Kalter

    IPC分类号： G06F11/00 ,  G06F11/10

    CPC分类号： G06F11/1052 ,  G06F11/1008

    摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which is tied to a system level error correction function, memory reliability is enhanced by providing a mechanism for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

    摘要翻译： 在包括多个存储器单元的存储器系统中，每个存储器单元具有单位级错误校正能力，并且每个都与系统级错误校正功能相关联，通过提供用于禁用单元级错误校正的机制来增强存储器的可靠性 能力，例如，响应于在一个存储器单元中发生不可校正的错误。 这种禁用纠错功能的反直觉方法仍然提高了整体存储系统的可靠性，因为它可以使用补充/重新补充算法，这取决于是否存在可重复的错误以进行正确的操作。 因此，在高封装密度下越来越需要的芯片级误差校正系统采用不干扰系统级误差校正方法的方式。

    Structure for differential eFUSE sensing without reference fuses
    3.
    发明授权
    Structure for differential eFUSE sensing without reference fuses 有权
    不带参考保险丝的差分eFUSE检测结构

    公开(公告)号：US07688654B2

    公开(公告)日：2010-03-30

    申请号：US11769925

    申请日：2007-06-28

    申请人： Darren Lane Anand ,  John Atkinson Fifield ,  Michael Richard Ouellette

    发明人： Darren Lane Anand ,  John Atkinson Fifield ,  Michael Richard Ouellette

    IPC分类号： G11C11/063

    CPC分类号： G11C17/16 ,  G11C17/18

    摘要： A design structure comprising a differential fuse sensing system, which includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.

    摘要翻译： 一种设计结构，包括差分熔丝感测系统，其包括被配置用于通过要被感测的电可编程熔丝（eFUSE）引入感测电流的熔丝腿，以及具有耦合到保险丝腿的第一输入节点的差分读出放大器和 耦合到参考电压的第二节点。 保险丝腿还包括由可变参考电流发生器控制的电流供应装置，其被配置为从其产生输出信号，使得读出放大器的第一输入节点上的电压等于读出放大器的第二输入节点上的电压 每当eFUSE的电阻值等于包括在可变参考电流发生器内的可编程可变电阻器件的电阻值时。

    Low-voltage differential amplifier
    4.
    发明授权
    Low-voltage differential amplifier 失效
    低压差分放大器

    公开(公告)号：US06975169B2

    公开(公告)日：2005-12-13

    申请号：US10707891

    申请日：2004-01-21

    申请人： John Atkinson Fifield ,  Steven Harley Lamphier

    发明人： John Atkinson Fifield ,  Steven Harley Lamphier

    IPC分类号： H03F3/45

    CPC分类号： H03F3/4521 ,  H03F3/45183 ,  H03F2200/513 ,  H03F2203/45366

    摘要： A low-voltage differential amplifier circuit is disclosed. The low-voltage differential amplifier circuit includes a first differential amplifier, a second differential amplifier and a summing circuit. The first differential amplifier receives a pair of differential input signals to generate a first output. The second differential amplifier receives the same pair of differential input signals to generate a second output. The summing circuit sums the first output of the first differential amplifier and the second output of the second differential amplifier to provide a common output.

    摘要翻译： 公开了一种低压差分放大器电路。 低压差分放大电路包括第一差分放大器，第二差分放大器和求和电路。 第一差分放大器接收一对差分输入信号以产生第一输出。 第二差分放大器接收同一对差分输入信号以产生第二输出。 求和电路将第一差分放大器的第一输出和第二差分放大器的第二输出相加以提供公共输出。

    Programmable DC voltage generator system
    6.
    发明授权
    Programmable DC voltage generator system 失效
    可编程直流电压发生器系统

    公开(公告)号：US06737907B2

    公开(公告)日：2004-05-18

    申请号：US09898328

    申请日：2001-07-03

    申请人： Louis L. Hsu ,  Li-Kong Wang ,  John Atkinson Fifield ,  Wayne F. Ellis

    发明人： Louis L. Hsu ,  Li-Kong Wang ,  John Atkinson Fifield ,  Wayne F. Ellis

    IPC分类号： G05F110

    CPC分类号： H02M3/073 ,  H02M2001/0012 ,  H02M2001/0025

    摘要： A digitally programmable DC voltage generator system having a programming circuit for controlling a control circuit of a voltage generator system. The programming circuit receives an input control signal, processes the input control signal, and generates an output control signal to the control circuit of the voltage generator system for controlling the control circuit in accordance with the input control signal. The control circuit includes a limiter circuit and an oscillator circuit. The output control signal controls at least one of the limiter circuit for disabling the oscillator circuit upon reaching a target output voltage, and the oscillator circuit for controlling the pumping speed of the oscillator circuit.

    摘要翻译： 一种具有用于控制电压发生器系统的控制电路的编程电路的数字可编程直流电压发生器系统。 编程电路接收输入控制信号，处理输入控制信号，并将输出控制信号产生到电压发生器系统的控制电路，用于根据输入控制信号控制控制电路。 控制电路包括限幅电路和振荡电路。 输出控制信号控制至少一个限制电路，用于在达到目标输出电压时使振荡器电路无效，以及用于控制振荡器电路的泵送速度的振荡器电路。

    Decode scheme for programming antifuses arranged in banks
    8.
    发明授权
    Decode scheme for programming antifuses arranged in banks 失效
    用于在银行中排列的编程反熔丝的解码方案

    公开(公告)号：US06339559B1

    公开(公告)日：2002-01-15

    申请号：US09781883

    申请日：2001-02-12

    申请人： Claude Louis Bertin ,  John Atkinson Fifield ,  Nicholas Martin van Heel

    发明人： Claude Louis Bertin ,  John Atkinson Fifield ,  Nicholas Martin van Heel

    IPC分类号： G11C1716

    CPC分类号： G11C17/16

    摘要： Described is an antifuse array comprising a plurality of antifuse elements and a plurality of cell plates. Each of the antifuse elements comprises a programming transistor and one of the cell plates. The programming transistor and the cell plate of each antifuse element are both activated to program the antifuse element. Each of the cell plates is coupled to a portion of the plurality of antifuse elements and to one of a plurality of decode circuits, and the decode circuits selectively activate its coupled cell plate. With a preferred embodiment, a multitude of interconnect lines are connected to the antifuses and in particular, each interconnect line intersects each of the cell plates and is associated with one antifuse in each group of antifuses. With this preferred embodiment, the array of antifuses are decoded by predecoding one of the cell plates by elevating the cell plate voltage from ground to a program voltage, and decoding one of the interconnect lines to program one of the antifuses. The intersection of the cell plate set to a program voltage and the decoded interconnect line results in programming a unique antifuse.

    摘要翻译： 描述了包括多个反熔丝元件和多个单元板的反熔丝阵列。 每个反熔丝元件包括编程晶体管和单元板之一。 每个反熔丝元件的编程晶体管和单元板都被激活以对反熔丝元件进行编程。 每个单元板耦合到多个反熔丝元件的一部分和多个解码电路中的一个，并且解码电路选择性地激活其耦合的单元板。 利用优选实施例，多个互连线连接到反熔丝，并且特别地，每个互连线与每个单元板相交，并且在每组反熔丝组中与一个反熔丝相关联。 利用该优选实施例，通过将单元板电压从地面升高到编程电压，对单元板中的一个进行预解码，并解码其中一条互连线以对其中一个反熔丝进行编译，对反熔丝阵列进行解码。 单元板设置为编程电压和解码的互连线的交点导致编程独特的反熔丝。

    Three device BICMOS gain cell
    9.
    发明授权
    Three device BICMOS gain cell 失效
    三器件BICMOS增益单元

    公开(公告)号：US5909400A

    公开(公告)日：1999-06-01

    申请号：US917630

    申请日：1997-08-22

    申请人： Claude Louis Bertin ,  John Atkinson Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

    发明人： Claude Louis Bertin ,  John Atkinson Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

    IPC分类号： G11C11/405 ,  G11C11/406 ,  G11C11/34

    CPC分类号： G11C11/406 ,  G11C11/405

    摘要： A nondestructive read, three device BICMOS gain cell for a DRAM memory having two FETs and one bipolar device. The gain cell has an improved access time (less latency), can operate for longer periods of time before a refresh operation is required, requires a smaller storage capacitance than a traditional DRAM cell, and can be produced commercially at lower costs than are presently available. In a preferred embodiment, the gain cell comprises an n channel metal oxide semiconductor field effect write transistor having its gate connected to a write word line WLw. Its drain is connected to a storage node Vs having a storage capacitance Cs associated therewith, and its source is connected to a write bit line BLw. An n channel metal oxide semiconductor field effect read transistor has its gate connected to the storage node Vs and its source connected to a read word line WLr. A PNP transistor has its base connected to the drain of the read transistor and its emitter connected to a read bit line BLr. A second embodiment is constructed with p channel FETs and an NPN transistor.

    摘要翻译： 具有两个FET和一个双极器件的DRAM存储器的非破坏性读取，三器件BICMOS增益单元。 增益单元具有改进的访问时间（更低的延迟），可以在需要刷新操作之前更长时间地操作，需要比传统DRAM单元更小的存储电容，并且可以以比目前可用的更低的成本在商业上生产 。 在优选实施例中，增益单元包括其栅极连接到写入字线WLw的n沟道金属氧化物半导体场效应写入晶体管。 其漏极连接到具有与其相关联的存储电容Cs的存储节点Vs，并且其源极连接到写入位线BLw。 n沟道金属氧化物半导体场效应读取晶体管的栅极连接到存储节点Vs，其源极连接到读取字线WLr。 PNP晶体管的基极连接到读晶体管的漏极，其发射极连接到读位线BLr。 第二实施例由p沟道FET和NPN晶体管构成。