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260 条记录 (耗时 0.034 秒)

    Three device BICMOS gain cell
    1.
    发明授权
    Three device BICMOS gain cell 失效
    三器件BICMOS增益单元

    公开(公告)号：US5909400A

    公开(公告)日：1999-06-01

    申请号：US917630

    申请日：1997-08-22

    申请人： Claude Louis Bertin ,  John Atkinson Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

    发明人： Claude Louis Bertin ,  John Atkinson Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

    IPC分类号： G11C11/405 ,  G11C11/406 ,  G11C11/34

    CPC分类号： G11C11/406 ,  G11C11/405

    摘要： A nondestructive read, three device BICMOS gain cell for a DRAM memory having two FETs and one bipolar device. The gain cell has an improved access time (less latency), can operate for longer periods of time before a refresh operation is required, requires a smaller storage capacitance than a traditional DRAM cell, and can be produced commercially at lower costs than are presently available. In a preferred embodiment, the gain cell comprises an n channel metal oxide semiconductor field effect write transistor having its gate connected to a write word line WLw. Its drain is connected to a storage node Vs having a storage capacitance Cs associated therewith, and its source is connected to a write bit line BLw. An n channel metal oxide semiconductor field effect read transistor has its gate connected to the storage node Vs and its source connected to a read word line WLr. A PNP transistor has its base connected to the drain of the read transistor and its emitter connected to a read bit line BLr. A second embodiment is constructed with p channel FETs and an NPN transistor.

    摘要翻译： 具有两个FET和一个双极器件的DRAM存储器的非破坏性读取，三器件BICMOS增益单元。 增益单元具有改进的访问时间（更低的延迟），可以在需要刷新操作之前更长时间地操作，需要比传统DRAM单元更小的存储电容，并且可以以比目前可用的更低的成本在商业上生产 。 在优选实施例中，增益单元包括其栅极连接到写入字线WLw的n沟道金属氧化物半导体场效应写入晶体管。 其漏极连接到具有与其相关联的存储电容Cs的存储节点Vs，并且其源极连接到写入位线BLw。 n沟道金属氧化物半导体场效应读取晶体管的栅极连接到存储节点Vs，其源极连接到读取字线WLr。 PNP晶体管的基极连接到读晶体管的漏极，其发射极连接到读位线BLr。 第二实施例由p沟道FET和NPN晶体管构成。

    Capacitive precharging and discharging network for converting N bit input into M bit output
    2.
    发明授权
    Capacitive precharging and discharging network for converting N bit input into M bit output 失效
    用于将N位输入转换为M位输出的电容式预充放电网络

    公开(公告)号：US06195027B1

    公开(公告)日：2001-02-27

    申请号：US09302744

    申请日：1999-04-30

    申请人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  Steven W. Tomashot ,  William R. Tonti

    发明人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  Steven W. Tomashot ,  William R. Tonti

    IPC分类号： H03M720

    CPC分类号： G11C8/10

    摘要： A method and structure for decoding n input signals and their complements to one of m output signals is provided. A capacitive network is provided having m output nodes. The output nodes are precharged to a given voltage value. N input signals and their complements are provided each having either a high value or a low value. At least one but less than all of the output nodes are discharged to a value less than the given voltage but greater than ground in output patterns responsive to given input patterns of the true and complement values of the input signals. The output patterns of the discharged nodes is such as to provide one and only one discharged or one and only one undischarged node for any given pattern of input signals. Preferably the capacitive network includes NMOS inversion capacitors.

    摘要翻译： 提供了用于将n个输入信号及其与m个输出信号之一的补码进行解码的方法和结构。 提供具有m个输出节点的电容网络。 输出节点预充电到给定的电压值。 提供N个输入信号及其补码，每个具有高值或低值。 响应于输入信号的真值和补码值的给定输入模式，至少一个但不到所有输出节点的输出模式被放电到小于给定电压但大于输出模式的输出值的值。 放电节点的输出模式是为任何给定模式的输入信号提供一个且仅一个放电或一个且仅一个未充电节点。 优选地，电容网络包括NMOS反转电容器。

    Multi-level storage gain cell with stepline
    3.
    发明授权
    Multi-level storage gain cell with stepline 失效
    带梯级的多级存储增益单元

    公开(公告)号：US5761114A

    公开(公告)日：1998-06-02

    申请号：US803034

    申请日：1997-02-19

    申请人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

    发明人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

    IPC分类号： G11C11/56

    CPC分类号： G11C11/565 ,  G11C16/30

    摘要： A method and apparatus for using multi-level signals in a gain cell is shown. The method involves of first, storing a value of a multi-level signal in the gain cell. A stepping waveform is then applied to the gain cell and the gain cell outputs a conduction signal when the level of the stepping waveform corresponds to the value of the multilevel signal that is stored within the gain cell. Finally, the value of the multi-level signal is determined through the conduction signal and the corresponding level of the stepping waveform. The gain cell includes an input device, a storage device and a level comparator, which responds to the stepping waveform generated from a stepping signal generator and outputs the conduction signal for determining the value of the multi-level signal stored in the storage device.

    摘要翻译： 示出了在增益单元中使用多电平信号的方法和装置。 该方法首先在增益单元中存储多电平信号的值。 然后，当增益单元的步进波形对应于存储在增益单元内的多电平信号的值时，增益单元输出导通信号。 最后，通过导通信号和步进波形的相应电平来确定多电平信号的值。 增益单元包括响应于从步进信号发生器产生的步进波形的输入装置，存储装置和电平比较器，并输出用于确定存储在存储装置中的多电平信号的值的导通信号。

    Module with low leakage driver circuits and method of operation
    4.
    发明授权
    Module with low leakage driver circuits and method of operation 失效
    具有低泄漏驱动电路的模块和操作方法

    公开(公告)号：US06268748B1

    公开(公告)日：2001-07-31

    申请号：US09073517

    申请日：1998-05-06

    申请人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

    发明人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

    IPC分类号： G03K19094

    CPC分类号： G11C7/1069 ,  G11C7/1051 ,  H03K19/0016 ,  H03K19/09429

    摘要： An electronic semiconductor module, either memory or logic, having a driver circuit which includes a multiplicity of driver transistors, together with circuitry for simultaneously applying a first positive bias to a first select number of driver transistors to activate them to an operational state, a second positive bias to a second select number of driver transistors to place them in readiness for activation, and a negative bias to the remaining driver transistors to place them in a fully inactive state thereby reducing noise in the driver circuit. The first positive bias is greater than the transistor threshold voltage, preferably greater than two volts, the second positive bias is less than the threshold voltage, preferably less than one volt, and the negative bias is in the order of minus 0.3 volt. A method of reducing noise in the electronic semiconductor module is also described and includes the applying of a positive bias to a first select number of the transistors to activate them while simultaneously applying a second positive bias to a second select number of the transistors to ready them for activation, and a negative voltage to the remaining transistors to place each in a inactive condition.

    摘要翻译： 一种电子半导体模块，无论是存储器还是逻辑，具有包括多个驱动器晶体管的驱动器电路，以及用于同时向第一选择数量的驱动器晶体管施加第一正偏置以将其激活到操作状态的电路，第二 对第二选择数量的驱动器晶体管施加正偏置以使它们准备激活，以及对其余驱动器晶体管的负偏置以将它们置于完全无效状态，从而降低驱动器电路中的噪声。 第一正偏压大于晶体管阈值电压，优选大于2伏，第二正偏压小于阈值电压，优选小于1伏特，负偏压为零下0.3伏。 还描述了降低电子半导体模块中的噪声的方法，并且包括将正偏压施加到第一选择数量的晶体管以激活它们，同时向第二选择数量的晶体管施加第二正偏置以准备它们 用于激活，并且向剩余晶体管施加负电压以使其处于非活动状态。

    Gain memory cell with diode
    5.
    发明授权
    Gain memory cell with diode 失效
    增益二极管存储单元

    公开(公告)号：US5757693A

    公开(公告)日：1998-05-26

    申请号：US803056

    申请日：1997-02-19

    申请人： Russell J. Houghton ,  Claude L. Bertin ,  John A. Fifield ,  Christopher P. Miller ,  William R. Tonti

    发明人： Russell J. Houghton ,  Claude L. Bertin ,  John A. Fifield ,  Christopher P. Miller ,  William R. Tonti

    IPC分类号： G11C11/402 ,  G11C11/403 ,  G11C11/405 ,  G11C11/24

    CPC分类号： G11C11/405 ,  G11C11/403

    摘要： A gain cell in a memory array having read and write bitlines and wordlines, wherein the gain cell comprises a write transistor, a storage node, a read transistor, and a diode is disclosed. The write transistor allows the value of the write bitline to be stored onto the storage node when activated by the write wordline. The read transistor, which allows the stored value to be read, is coupled to the storage node and to the read bitline via the diode. The diode prevents the conduction of the read transistor in the opposite direction, thus preventing read interference from other cells and reducing bitline capacitance.

    摘要翻译： 具有读和写位线和字线的存储器阵列中的增益单元，其中增益单元包括写晶体管，存储节点，读晶体管和二极管。 当由写入字线激活时，写入晶体管允许将写入位线的值存储到存储节点上。 允许读取存储值的读取晶体管通过二极管耦合到存储节点和读取位线。 二极管防止读取晶体管在相反方向的导通，从而防止来自其他单元的读取干扰并减少位线电容。

    High impedance antifuse
    9.
    发明授权
    High impedance antifuse 失效
    高阻抗反熔丝

    公开(公告)号：US07098083B2

    公开(公告)日：2006-08-29

    申请号：US10652534

    申请日：2003-08-29

    申请人： John A. Fifield ,  Russell J. Houghton ,  William R. Tonti

    发明人： John A. Fifield ,  Russell J. Houghton ,  William R. Tonti

    IPC分类号： H01L21/82

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S438/957 ,  H01L2924/00

    摘要： A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.

    摘要翻译： 一种可编程元件，其具有第一二极管，其具有电极和设置在所述基板和所述第一器件的所述电极之间的第一绝缘体，所述第一绝缘体具有给定特性的第一值，以及设置有电极和第二绝缘体的FET 在所述基板和所述第二装置的所述电极之间，所述第二绝缘体具有与所述第一值不同的所述给定特性的第二值。 二极管和FET的电极彼此耦合，并且编程能量源耦合到二极管，以使其在编程时永久地降低电阻率。 二极管的编程状态由FET中的电流表示，该电流由读出锁存器读取。 因此，二极管中的小电阻变化转换为锁存器中的大信号增益/变化。 这允许二极管在较低的电压下被编程。

    Single-ended semiconductor receiver with built in threshold voltage difference
    10.
    发明授权
    Single-ended semiconductor receiver with built in threshold voltage difference 失效
    单端半导体接收器内置阈值电压差

    公开(公告)号：US06222395B1

    公开(公告)日：2001-04-24

    申请号：US09225112

    申请日：1999-01-04

    申请人： Claude L. Bertin ,  Russell J. Houghton ,  William R. Tonti

    发明人： Claude L. Bertin ,  Russell J. Houghton ,  William R. Tonti

    IPC分类号： G05F110

    CPC分类号： G05F3/205

    摘要： A differential receiver for sensing small input voltage swings by using a built in reference voltage obtained by a difference in threshold voltage between a differential pair of closely spaced transistors. The difference in threshold voltage can be produced by different values of ion implantation of the gates of the transistor pair with the same material, or by dosages using different materials. The difference in threshold voltage can also be obtained by using different transistor channel lengths. The threshold voltages can also be modulated by the control of the transistor substrate voltages using a voltage control substrate means.

    摘要翻译： 一种差分接收器，用于通过使用通过差分对间隔晶体管之间的阈值电压差而获得的内置参考电压来感测小输入电压摆幅。 阈值电压的差异可以通过使用相同材料的晶体管对的栅极的离子注入的不同值，或通过使用不同材料的剂量来产生。 也可以通过使用不同的晶体管沟道长度来获得阈值电压的差异。 也可以通过使用电压控制衬底装置控制晶体管衬底电压来调制阈值电压。