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19 条记录 (耗时 0.019 秒)

    Low power on-chip global interconnects
    1.
    发明授权
    Low power on-chip global interconnects 失效
    低功耗片上全局互连

    公开(公告)号：US07545205B2

    公开(公告)日：2009-06-09

    申请号：US11924791

    申请日：2007-10-26

    申请人： Robin Tang ,  Ephrem C. Wu

    发明人： Robin Tang ,  Ephrem C. Wu

    IPC分类号： H01L25/00

    CPC分类号： G11C7/1048 ,  G11C11/413

    摘要： An apparatus including a first circuit, a second circuit and a third circuit. The first circuit may be configured to (a) receive (i) a plurality of input signals and (ii) a clock signal and (b) present (i) a plurality of low-swing differential signals and (ii) a full-swing differential signal. The second circuit may be configured to (a) receive (i) the plurality of low-swing differential signals, (ii) the full-swing differential signal and (iii) the clock signal and (b) present a plurality of output signals. The third circuit may be configured to communicate the plurality of low-swing differential signals and the full-swing differential signal from the first circuit to the second circuit. The third circuit may be further configured to generate a local clock in response to the full-swing differential signal.

    摘要翻译： 一种包括第一电路，第二电路和第三电路的装置。 第一电路可以被配置为（a）接收（i）多个输入信号和（ii）时钟信号，以及（b）存在（i）多个低摆幅差分信号和（ii）全摆幅 差分信号。 第二电路可以被配置为（a）接收（i）多个低摆幅差分信号，（ii）全摆幅差分信号和（iii）时钟信号和（b）呈现多个输出信号。 第三电路可以被配置为将多个低摆幅差分信号和全摆幅差分信号从第一电路传送到第二电路。 第三电路还可以被配置为响应于全摆幅差分信号而产生本地时钟。

    LOW POWER ON-CHIP GLOBAL INTERCONNECTS
    2.
    发明申请
    LOW POWER ON-CHIP GLOBAL INTERCONNECTS 失效
    低功率片上全球互连

    公开(公告)号：US20090108925A1

    公开(公告)日：2009-04-30

    申请号：US11924791

    申请日：2007-10-26

    申请人： Robin Tang ,  Ephrem C. Wu

    发明人： Robin Tang ,  Ephrem C. Wu

    IPC分类号： H04B1/10

    CPC分类号： G11C7/1048 ,  G11C11/413

    摘要： An apparatus including a first circuit, a second circuit and a third circuit. The first circuit may be configured to (a) receive (i) a plurality of input signals and (ii) a clock signal and (b) present (i) a plurality of low-swing differential signals and (ii) a full-swing differential signal. The second circuit may be configured to (a) receive (i) the plurality of low-swing differential signals, (ii) the full-swing differential signal and (iii) the clock signal and (b) present a plurality of output signals. The third circuit may be configured to communicate the plurality of low-swing differential signals and the full-swing differential signal from the first circuit to the second circuit. The third circuit may be further configured to generate a local clock in response to the full-swing differential signal.

    摘要翻译： 一种包括第一电路，第二电路和第三电路的装置。 第一电路可以被配置为（a）接收（i）多个输入信号和（ii）时钟信号，以及（b）存在（i）多个低摆幅差分信号和（ii）全频 差分信号。 第二电路可以被配置为（a）接收（i）多个低摆幅差分信号，（ii）全摆幅差分信号和（iii）时钟信号和（b）呈现多个输出信号。 第三电路可以被配置为将多个低摆幅差分信号和全摆幅差分信号从第一电路传送到第二电路。 第三电路还可以被配置为响应于全摆幅差分信号而产生本地时钟。

    Interconnects using Self-timed Time-Division Multiplexed Bus
    3.
    发明申请
    Interconnects using Self-timed Time-Division Multiplexed Bus 有权
    互连使用自定时分复用总线

    公开(公告)号：US20110211582A1

    公开(公告)日：2011-09-01

    申请号：US13123124

    申请日：2008-11-19

    申请人： Ting Zhou ,  Robin J. Tang ,  Ephrem C. Wu ,  Tezaswi Raja

    发明人： Ting Zhou ,  Robin J. Tang ,  Ephrem C. Wu ,  Tezaswi Raja

    IPC分类号： H04J3/06 ,  H04L12/56

    CPC分类号： G06F13/4221 ,  Y02D10/14 ,  Y02D10/151

    摘要： A method of sending signals, including data and timing information, between transportation units on a communication bus of an integrated circuit, by generating clock triggers for every transportation unit on the bus, thereby initiating each preceding one of the transportation units to start sending the signals in a wave-front to an adjacent succeeding one of the transportation units, where the wave-front is initiated at each of the transportation units at a common point in time, and every transportation unit applying a timing adjustment to at least one of the data and timing information that it receives in the signals from the preceding transportation unit, to at least one of (1) capture the data from the preceding transportation unit, (2) relay the data without modification from the preceding transportation unit to the succeeding transportation unit on the communication bus, and (3) load new data to the communication bus, with updated timing information in a succeeding wave-front.

    摘要翻译： 一种在集成电路的通信总线上的传送单元之间发送信号（包括数据和定时信息）的方法，通过为总线上的每个传送单元生成时钟触发，从而启动每个前一个传输单元以开始发送信号 在相邻的后一个运输单元的波前，其中波前在公共时间点在每个运输单元处开始，并且每个运输单元对至少一个数据施加定时调整 （1）捕获来自前一个运输单元的数据中的至少一个，（2）将来自前一个运输单元的数据从前一个运输单元传送到后续运输单元 在通信总线上，以及（3）将新数据加载到通信总线，并在随后的波前更新定时信息。

    Digital cross-connect
    4.
    发明授权
    Digital cross-connect 有权
    数字交叉连接

    公开(公告)号：US07349387B2

    公开(公告)日：2008-03-25

    申请号：US10341546

    申请日：2003-01-13

    申请人： Ephrem C. Wu

    发明人： Ephrem C. Wu

    IPC分类号： H04L12/50

    CPC分类号： H04J3/1611 ,  H04Q3/521 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13076 ,  H04Q2213/13103 ,  H04Q2213/13322

    摘要： Two or more cross-connect ICs are interconnected. Each IC directly receives some, but not all, of the system inputs, and outputs to some, but not all, outputs. Each cross-connect IC has a switch matrix that has the same number of inputs as the system, and a lesser number of outputs that matches the number of outputs of the IC. Each cross-connect IC provides fanout of its direct inputs to a link to each other cross-connect IC. Thus, each IC receives inputs either directly, or from a fanout on another IC.

    摘要翻译： 两个或更多个交叉连接IC互连。 每个IC直接接收一些但不是全部的系统输入，并输出到一些但不是全部的输出。 每个交叉连接IC具有与系统相同数量的输入的开关矩阵，以及与IC的输出数量匹配的较少数量的输出。 每个交叉连接IC提供其直接输入的扇出到彼此交叉连接IC的链路。 因此，每个IC直接或从另一个IC上的扇出接收输入。

    Stacked die assembly
    5.
    发明授权
    Stacked die assembly 有权
    堆叠模组件

    公开(公告)号：US08704384B2

    公开(公告)日：2014-04-22

    申请号：US13399939

    申请日：2012-02-17

    申请人： Ephrem C. Wu ,  Raghunandan Chaware

    发明人： Ephrem C. Wu ,  Raghunandan Chaware

    IPC分类号： H01L23/48 ,  H01L21/56

    CPC分类号： H01L24/17 ,  H01L23/147 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/1712 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/00

    摘要： A stacked die assembly for an IC includes a first interposer; a second interposer; a first integrated circuit die, a second integrated circuit die, and a plurality of components. The first integrated circuit die is interconnected to the first interposer and the second interposer, and the second integrated circuit die is interconnected to the second interposer. The plurality of components interconnect the first integrated circuit die to the first interposer and the second interposer. The plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area of the first interposer and the second interposer, and signals are routed between the first integrated circuit die and the second integrated circuit die via the first integrated circuit die avoiding the interconnect restricted area of the first interposer and the second interposer.

    摘要翻译： 用于IC的堆叠式芯片组件包括：第一插入件; 第二插值器; 第一集成电路管芯，第二集成电路管芯和多个部件。 第一集成电路管芯与第一插入件和第二插入件相互连接，第二集成电路管芯与第二插入件互连。 多个部件将第一集成电路管芯与第一插入件和第二插入件互连。 将第一集成电路管芯与第一插入件和第二插入件互连的多个部件位于第一插入器和第二插入器的互连限制区域的外部，并且信号在第一集成电路管芯和第二集成电路之间布线 通过第一集成电路管芯，避免第一插入件和第二插入件的互连限制区域。

    CONTENTION-FREE MEMORY ARRANGEMENT
    6.
    发明申请
    CONTENTION-FREE MEMORY ARRANGEMENT 有权
    无内存安排

    公开(公告)号：US20130148450A1

    公开(公告)日：2013-06-13

    申请号：US13314079

    申请日：2011-12-07

    申请人： Ephrem C. Wu ,  Gyanesh Saharia

    发明人： Ephrem C. Wu ,  Gyanesh Saharia

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/1075 ,  G11C5/04 ,  G11C29/023 ,  G11C29/028

    摘要： A memory arrangement includes a plurality of memory blocks, a first group of access ports, and a second group of access ports. Routing circuitry couples each pair of the first and second groups of access ports to a respective one of the memory blocks. Each pair includes a first access port from the first group and a second access port from the second group. The first access port has write access to a first portion of the respective memory blocks but not to a second portion of the memory block, and has read access to the second portion but not to the first portion. The second access port has write access to the second portion but not to the first portion, and has read access to the first portion but not to the second portion.

    摘要翻译： 存储器装置包括多个存储器块，第一组访问端口和第二组访问端口。 路由电路将每对第一和第二组接入端口耦合到相应的一个存储块。 每对包括来自第一组的第一访问端口和来自第二组的第二访问端口。 第一访问端口具有对相应存储器块的第一部分的写入访问，但不具有对存储器块的第二部分的写入访问，并且具有对第二部分的读取访问，而不具有对第一部分的读取访问。 第二访问端口具有对第二部分的写入访问，但不具有对第一部分的写入访问，并且具有对第一部分的读取访问权限，而不具有对第二部分的读取访问。

    INTERPOSER HAVING AN INDUCTOR
    7.
    发明申请
    INTERPOSER HAVING AN INDUCTOR 有权
    具有电感器的插座

    公开(公告)号：US20120248569A1

    公开(公告)日：2012-10-04

    申请号：US13075059

    申请日：2011-03-29

    申请人： Michael O. Jenkins ,  James Karp ,  Vassili Kireev ,  Ephrem C. Wu

    发明人： Michael O. Jenkins ,  James Karp ,  Vassili Kireev ,  Ephrem C. Wu

    IPC分类号： H01L27/06

    CPC分类号： H01L23/645 ,  H01L23/49822 ,  H01L23/60 ,  H01L23/642 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

    摘要： An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures.

    摘要翻译： 公开了一种多芯片模块的实施例。 对于多芯片模块的该实施例，包括半导体管芯和插入件。 插入器具有导电层，电介质层和衬底。 内部互连结构将半导体管芯耦合到插入器。 外部互连结构用于将插入器耦合到外部设备。 第一电感器包括插入器的一个或多个导电层的至少一部分。 第一电感器的第一端耦合到内部互连结构的内部互连结构。 第一电感器的第二端耦合到外部互连结构的外部互连结构。

    Multi-die stack package
    10.
    发明授权
    Multi-die stack package 有权
    多芯片堆栈封装

    公开(公告)号：US08546955B1

    公开(公告)日：2013-10-01

    申请号：US13587716

    申请日：2012-08-16

    申请人： Ephrem C. Wu

    发明人： Ephrem C. Wu

    IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

    CPC分类号： H01L23/5384 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/00014

    摘要： An embodiment of an apparatus is disclosed. This embodiment of the apparatus includes an interposer, a first die stack, a second die stack, a third die stack, and a fourth die stack which are all coupled to the interposer. The interposer provides a common base for and a stratum of each of the first die stack, the second die stack, the third die stack, and the fourth die stack. The first die stack includes an optical engine. The optical engine includes at least one optical engine die. The second die stack includes a plurality of programmable resource dies. The third die stack includes at least one memory die. The fourth die stack includes a serializer-deserializer die.

    摘要翻译： 公开了一种装置的实施例。 该装置的该实施例包括全部耦合到插入器的插入器，第一管芯堆叠，第二管芯堆叠，第三管芯堆叠和第四管芯堆叠。 插入器为第一管芯堆叠，第二管芯堆叠，第三管芯堆叠和第四管芯堆叠中的每一个提供共同的基底和层。 第一模具堆叠包括光学引擎。 光学引擎包括至少一个光学引擎模具。 第二管芯堆叠包括多个可编程资源管芯。 第三管芯堆叠包括至少一个存储管芯。 第四个模块堆叠包括串行器 - 解串器模块。