公开(公告)号：US20090213565A1

公开(公告)日：2009-08-27

申请号：US12038356

申请日：2008-02-27

申请人： Roger A. Booth, Jr. ,  John M. Dangler ,  Matthew S. Doyle

发明人： Roger A. Booth, Jr. ,  John M. Dangler ,  Matthew S. Doyle

IPC分类号： H05K9/00 ,  H01R43/00

CPC分类号： H05K1/0218 ,  H05K3/403 ,  H05K2201/0355 ,  H05K2201/056 ,  H05K2201/0715 ,  Y10T29/49117

摘要： Exemplary embodiments of the present invention relate to a method for making multilayer flexible printed circuit carrier. The method comprises producing a first flexible conductor layer having a first width, producing a second flexible conductor layer having a second width larger than the first width, and separating a first side of the first flexible conductor and a first side of the second flexible conductors with a first insulator. The method also comprises placing a second insulator over at least a portion of a second surface of the first flexible conductor, and wrapping a portion of the second flexible conductor over the at least a portion of the second surface of the first flexible conductor.

摘要翻译： 本发明的示例性实施例涉及制造多层柔性印刷电路载体的方法。 该方法包括制造具有第一宽度的第一柔性导体层，产生具有大于第一宽度的第二宽度的第二柔性导体层，以及将第一柔性导体的第一侧和第二柔性导体的第一侧分别与 第一绝缘体。 该方法还包括将第二绝缘体放置在第一柔性导体的第二表面的至少一部分上，以及将第二柔性导体的一部分包裹在第一柔性导体的第二表面的至少一部分上。

公开(公告)号：US07525299B1

公开(公告)日：2009-04-28

申请号：US12163346

申请日：2008-06-27

申请人： Paul W. Rudrud ,  Roger A. Booth, Jr. ,  John R. Dangler ,  Matthew S. Doyle ,  Jesse M. Hefner ,  Ankur K. Patel ,  Thomas W. Liang

发明人： Paul W. Rudrud ,  Roger A. Booth, Jr. ,  John R. Dangler ,  Matthew S. Doyle ,  Jesse M. Hefner ,  Ankur K. Patel ,  Thomas W. Liang

IPC分类号： G01R31/02

CPC分类号： G01R31/2812 ,  G01R31/046

摘要： A device to access and/or verify connections between a chip package and a printed circuit board (“PCB”), specifically within packages lacking back-side measurement access, includes a housing for insertion between the chip package and PCB. A passageway in the housing connects an entrance and an exit from the housing. The entrance is disposed on an end of the housing facing away from the chip package. The exit is disposed on a side of the housing below the chip package such that the passageway is directed at a signal path between the chip package and the PCB. A conductor disposed in the passageway is movable between a retracted position in which a contact end of the conductor is disposed within the passageway of the housing and an extended position in which the contact end of the conductor is disposed outside of the housing and in contact with the signal path.

摘要翻译： 访问和/或验证芯片封装和印刷电路板（“PCB”）之间的连接的装置，特别是在没有背面测量通路的封装中，包括用于插入芯片封装和PCB之间的壳体。 壳体中的通道连接入口和出口与壳体。 入口设置在壳体的远离芯片封装的一端。 出口设置在芯片封装下方的壳体的一侧，使得通道指向芯片封装和PCB之间的信号路径。 设置在通道中的导体可在缩回位置之间移动，在该缩回位置，导体的接触端设置在壳体的通道内，并且延伸位置，其中导体的接触端设置在壳体的外部并与其接触 信号路径。

公开(公告)号：US20090056998A1

公开(公告)日：2009-03-05

申请号：US11848330

申请日：2007-08-31

申请人： Roger A. Booth, Jr. ,  John R. Dangler ,  Matthew S. Doyle ,  Jesse Hefner ,  Thomas W. Liang ,  Ankur K. Patel ,  Paul Rudrud

发明人： Roger A. Booth, Jr. ,  John R. Dangler ,  Matthew S. Doyle ,  Jesse Hefner ,  Thomas W. Liang ,  Ankur K. Patel ,  Paul Rudrud

IPC分类号： H05K1/11 ,  H05K3/10

CPC分类号： H05K3/429 ,  H05K1/0222 ,  H05K1/115 ,  H05K2201/09536 ,  H05K2201/09809 ,  H05K2203/061 ,  Y10T29/49165

摘要： Disclosed herein is a method comprising drilling a first hole in a multilayered device; the multilayered device comprising a fill layer disposed between and in intimate contact with two layers of a first electrically conducting material; the fill layer being electrically insulating; plating the first hole with a slurry; the slurry comprising a magnetic material, an electrically conducting material, or a combination comprising at least one of the foregoing materials; filling the first hole with a fill material; the fill material being electrically insulating; laminating a first layer and a second layer on opposing faces of the multilayered device to form a laminate; the opposing faces being the faces through which the first hole is drilled; the first layer and the second layer each comprising a second electrically conducting material; drilling a second hole through the laminate; the second hole having a circumference that is encompassed by a circumference of the first hole; and plating the surface of the second hole with a third electrically conducting material.

摘要翻译： 本文公开了一种方法，包括在多层装置中钻出第一孔; 所述多层器件包括设置在两层第一导电材料之间并与之紧密接触的填充层; 填充层电绝缘; 用浆料电镀第一个孔; 所述浆料包括磁性材料，导电材料或包含至少一种前述材料的组合; 用填充材料填充第一个孔; 填充材料电绝缘; 在所述多层器件的相对面上层叠第一层和第二层以形成层压体; 相对的面是钻出第一孔的面; 所述第一层和所述第二层各自包括第二导电材料; 穿过层压板钻出第二个孔; 所述第二孔具有由所述第一孔的圆周包围的圆周; 以及用第三导电材料电镀所述第二孔的表面。

公开(公告)号：US08691697B2

公开(公告)日：2014-04-08

申请号：US12943956

申请日：2010-11-11

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： H01L21/31056 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate.

摘要翻译： 一种方法包括在具有预定间距的基底上形成图案线。 该方法还包括在图案化线的侧壁上形成间隔壁。 该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。 该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。 该方法还包括将图案化线和另一图案化线的图案转移到衬底。

公开(公告)号：US08242549B2

公开(公告)日：2012-08-14

申请号：US12700807

申请日：2010-02-05

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L28/91 ,  H01L21/823431 ,  H01L27/10823 ,  H01L27/1085 ,  H01L27/10876 ,  H01L27/10879 ,  H01L28/60 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor fin having a doping of the first conductivity type and a semiconductor column are formed on a substrate. The semiconductor column and an adjoined end portion of the semiconductor fin are doped with dopants of a second conductivity type, which is the opposite of the first conductivity type. The doped semiconductor column constitutes an inner electrode of a capacitor. A dielectric layer and a conductive material layer are formed on the semiconductor fin and the semiconductor column. The conductive material layer is patterned to form an outer electrode for the capacitor and a gate electrode. A single-sided halo implantation may be performed. Source and drain regions are formed in the semiconductor fin to form an access transistor. The source region is electrically connected to the inner electrode of the capacitor. The access transistor and the capacitor collectively constitute a DRAM cell.

摘要翻译： 在衬底上形成具有第一导电类型掺杂的半导体鳍和半导体柱。 所述半导体柱和所述半导体鳍片的邻接端部掺杂有与所述第一导电类型相反的第二导电类型的掺杂剂。 掺杂半导体柱构成电容器的内部电极。 在半导体鳍片和半导体柱上形成介电层和导电材料层。 图案化导电材料层以形成用于电容器的外部电极和栅电极。 可以进行单侧晕圈植入。 源极和漏极区域形成在半导体鳍片中以形成存取晶体管。 源极区域电连接到电容器的内部电极。 存取晶体管和电容器共同构成DRAM单元。

公开(公告)号：US08030736B2

公开(公告)日：2011-10-04

申请号：US12538381

申请日：2009-08-10

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman

IPC分类号： H01L23/52 ,  H01L21/82

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method forms an anti-fuse structure comprises a plurality of parallel conductive fins positioned on a substrate, each of the fins has a first end and a second end. A second electrical conductor is electrically connected to the second end of the fins. An insulator covers the first end of the fins and a first electrical conductor is positioned on the insulator. The first electrical conductor is electrically insulated from the first end of the fins by the insulator. The insulator is formed to a thickness sufficient to break down on the application of a predetermined voltage between the second electrical conductor and the first electrical conductor and thereby form an uninterrupted electrical connection between the second electrical conductor and the first electrical conductor through the fins.

摘要翻译： 一种形成抗熔丝结构的方法包括位于基板上的多个平行的导电翅片，每个翼片具有第一端和第二端。 第二电导体电连接到散热片的第二端。 绝缘体覆盖翅片的第一端并且第一电导体位于绝缘体上。 第一电导体通过绝缘体与散热片的第一端电绝缘。 绝缘体形成为足以在第二电导体和第一电导体之间施加预定电压时分解的厚度，从而通过翅片在第二电导体和第一电导体之间形成不间断的电连接。

公开(公告)号：US08564069B1

公开(公告)日：2013-10-22

申请号：US13590212

申请日：2012-08-21

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/027 ,  H01L29/0615 ,  H01L29/78

摘要： Embodiments of the invention relate generally to semiconductor devices and, more particularly, to semiconductor devices having field effect transistors (FETs) with a low body resistance and, in some embodiments, a self-balanced body potential where multiple transistors share same body potential. In one embodiment, the invention includes a field effect transistor (FET) comprising a source within a substrate, a drain within the substrate, and an active gate atop the substrate and between the source and the drain, an inactive gate structure atop the substrate and adjacent the source or the drain, a body adjacent the inactive gate, and a discharge path within the substrate for releasing a charge from the FET, the discharge path lying between the active gate of the FET and the body, wherein the discharge path is substantially perpendicular to a width of the active gate.

摘要翻译： 本发明的实施例大体上涉及半导体器件，更具体地，涉及具有低体电阻的场效应晶体管（FET）的半导体器件，在一些实施例中，具有多个晶体管共享相同体电位的自平衡体电位。 在一个实施例中，本发明包括场效应晶体管（FET），其包括在衬底内的源极，衬底内的漏极，以及位于衬底顶部和源极与漏极之间的有源栅极，在衬底顶部的非活性栅极结构， 邻近源极或漏极，与非活性栅极相邻的主体以及衬底内的用于从FET释放电荷的放电路径，放电路径位于FET的有源栅极和主体之间，其中放电路径基本上 垂直于有源栅极的宽度。

公开(公告)号：US08481397B2

公开(公告)日：2013-07-09

申请号：US12719289

申请日：2010-03-08

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Rainer Loesing ,  Chengwen Pei ,  Xiaojun Yu

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Rainer Loesing ,  Chengwen Pei ,  Xiaojun Yu

IPC分类号： H01L21/20

CPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/525 ,  H01L29/12 ,  H01L29/86 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance. In a variation thereof, an electrical fuse is formed which includes a continuous silicide region through which a current can be passed to blow the fuse. Some of the steps of fabricating the poly resistor or the electrical fuse can be employed simultaneously in fabricating metal gate field effect transistors (FETs) on the same substrate.

摘要翻译： 提供了一种用于制造电阻性多晶半导体器件的方法，例如诸如半导体集成电路的微电子元件的多晶硅电阻器。 该方法可以包括：（a）形成层叠堆叠，其包括与衬底的单晶半导体区域的表面接触的电介质层，覆盖在电介质层上的金属栅极层，与金属栅极层相邻的第一多晶半导体区域， 掺杂剂类型的n或p，以及第二多晶半导体区域，其与所述第一多晶半导体区域与所述金属栅极层隔开并邻接所述第一多晶半导体区域; 和（b）形成与所述第二多晶半导体区域导电连通的第一和第二触点，所述第一和第二触点间隔开以达到期望的电阻。 在其变型中，形成电熔丝，其包括连续的硅化物区域，电流可以通过该硅化物区域通过以熔断熔丝。 在同一衬底上制造金属栅极场效应晶体管（FET）的同时可以同时采用制造多晶硅电阻器或电熔丝的步骤。

公开(公告)号：US08299530B2

公开(公告)日：2012-10-30

申请号：US12717375

申请日：2010-03-04

申请人： Chengwen Pei ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

发明人： Chengwen Pei ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/12 ,  H01L21/8238

CPC分类号： H01L21/22 ,  H01L21/8238 ,  H01L27/092

摘要： A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing.

摘要翻译： 提供了一种半导体结构及其形成方法，其中通过在pFET的选定部分内引入功函数调谐物质来控制栅极感应漏极泄漏，使得pFET的栅极/ SD（源极/漏极）重叠区域为 适应平带，但不影响设备通道区域的功能。 该结构包括具有位于半导体衬底的pFET器件区域内的至少一个图案化栅叠层的半导体衬底。 所述结构还包括位于所述半导体衬底内的所述至少一个图案化栅叠层的覆盖区的扩展区。 沟道区域也存在并且位于至少一个图案化栅叠层下方的半导体衬底内。 该结构进一步包括位于至少一个延伸区域的一部分内的局部功能调谐区域，其位于邻近通道区域以及至少一个栅极叠层的至少一个侧壁部分内。 通过离子注入或退火可形成局部功能调谐区域。

公开(公告)号：US07825479B2

公开(公告)日：2010-11-02

申请号：US12187003

申请日：2008-08-06

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei ,  Ravi M. Todi ,  Xiaojun Yu

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei ,  Ravi M. Todi ,  Xiaojun Yu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L23/5252 ,  H01L27/11206 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical antifuse comprising a field effect transistor includes a gate dielectric having two gate dielectric portions. Upon application of electric field across the gate dielectric, the magnitude of the electrical field is locally enhanced at the boundary between the thick and thin gate dielectric portions due to the geometry, thereby allowing programming of the electrical antifuse at a lower supply voltage between the two electrodes, i.e., the body and the gate electrode of the transistor, across the gate dielectric.

摘要翻译： 包括场效应晶体管的电反熔丝包括具有两个栅电介质部分的栅极电介质。 在栅极电介质上施加电场时，由于几何形状，在厚和薄栅介质部分之间的边界处，电场的幅度被局部增强，从而允许在两个电源电压之间的较低电源电压下对电反熔丝进行编程 电极，即晶体管的主体和栅电极，跨过栅极电介质。