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公开(公告)号:US20220190135A1
公开(公告)日:2022-06-16
申请号:US17117337
申请日:2020-12-10
申请人: Roza Kotlyar , Stephanie A. Bojarski , Hubert C. George , Payam Amin , Patrick H. Keys , Ravi Pillarisetty , Roman Caudillo , Florian Luethi , James S. Clarke
发明人: Roza Kotlyar , Stephanie A. Bojarski , Hubert C. George , Payam Amin , Patrick H. Keys , Ravi Pillarisetty , Roman Caudillo , Florian Luethi , James S. Clarke
IPC分类号: H01L29/49 , H01L29/06 , H01L29/423 , H01L29/15 , G06N10/00
摘要: Disclosed herein are lateral gate material arrangements for quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; and a gate above the quantum well stack, wherein the gate includes a gate electrode, the gate electrode includes a first material proximate to side faces of the gate and a second material proximate to a center of the gate, and the first material has a different material composition than the second material.
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公开(公告)号:US20140061589A1
公开(公告)日:2014-03-06
申请号:US14057204
申请日:2013-10-18
申请人: Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人: Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
IPC分类号: H01L29/775
CPC分类号: H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
摘要翻译: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。
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公开(公告)号:US20110156005A1
公开(公告)日:2011-06-30
申请号:US12655468
申请日:2009-12-30
申请人: Ravi Pillarisetty , Been-Yih Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人: Ravi Pillarisetty , Been-Yih Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
IPC分类号: H01L29/772
CPC分类号: H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
摘要翻译: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。
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公开(公告)号:US20120153387A1
公开(公告)日:2012-06-21
申请号:US12975278
申请日:2010-12-21
申请人: Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
发明人: Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
IPC分类号: H01L29/78 , H01L21/336
CPC分类号: H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
摘要翻译: 公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。 在一些实施例中,使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。 在一些这样的情况下,锗浓度可以例如超过50原子%且高达100原子%,并且硼浓度可以例如超过1E20cm-3。 可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。 锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。 这些技术可以例如在平面或非平面晶体管器件中实现。
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公开(公告)号:US20180226509A1
公开(公告)日:2018-08-09
申请号:US15747925
申请日:2015-07-31
申请人: Elijah V. Karpov , Prashant Majhi , Roza Kotlyar , Niloy Mukherjee , Charles C. Kuo , Uday Shah , Ravi Pillarisetty , Robert S. Chau
发明人: Elijah V. Karpov , Prashant Majhi , Roza Kotlyar , Niloy Mukherjee , Charles C. Kuo , Uday Shah , Ravi Pillarisetty , Robert S. Chau
IPC分类号: H01L29/786 , H01L27/07 , H01L27/12 , H01L29/49 , H01L29/02
CPC分类号: H01L29/7869 , H01L27/0705 , H01L27/1225 , H01L27/2436 , H01L29/02 , H01L29/4908 , H01L29/78603 , H01L29/78642 , H01L45/04 , H01L45/1206 , H01L45/1233 , H01L45/145 , H01L45/146
摘要: A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.
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公开(公告)号:US20150060945A1
公开(公告)日:2015-03-05
申请号:US14535387
申请日:2014-11-07
申请人: Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
发明人: Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
CPC分类号: H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
摘要翻译: 公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。 在一些实施例中,使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。 在一些这样的情况下,锗浓度可以例如超过50原子%且高达100原子%,并且硼浓度可以例如超过1E20cm-3。 可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。 锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。 这些技术可以例如在平面或非平面晶体管器件中实现。
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公开(公告)号:US08901537B2
公开(公告)日:2014-12-02
申请号:US12975278
申请日:2010-12-21
申请人: Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
发明人: Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
IPC分类号: H01L21/285 , H01L29/165 , H01L29/167 , H01L29/49 , H01L29/78 , H01L29/66 , H01L29/45
CPC分类号: H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
摘要翻译: 公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。 在一些实施例中,使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。 在一些这样的情况下,锗浓度可以例如超过50原子%且高达100原子%,并且硼浓度可以例如超过1E20cm-3。 可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。 锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。 这些技术可以例如在平面或非平面晶体管器件中实现。
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公开(公告)号:US08592803B2
公开(公告)日:2013-11-26
申请号:US13442098
申请日:2012-04-09
申请人: Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人: Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
IPC分类号: H01L29/06 , H01L29/778
CPC分类号: H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
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公开(公告)号:US20120193609A1
公开(公告)日:2012-08-02
申请号:US13442098
申请日:2012-04-09
申请人: Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人: Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
IPC分类号: H01L29/66
CPC分类号: H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
摘要翻译: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。
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公开(公告)号:US08193523B2
公开(公告)日:2012-06-05
申请号:US12655468
申请日:2009-12-30
申请人: Ravi Pillarisetty , Been-Yih Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人: Ravi Pillarisetty , Been-Yih Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
CPC分类号: H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
摘要翻译: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅介电材料允许使用高k值栅极电介质。
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