公开(公告)号：US08632691B2

公开(公告)日：2014-01-21

申请号：US13702562

申请日：2012-06-14

申请人： Ru Huang ,  Min Li ,  Xia An ,  Ming Li ,  Meng Lin ,  Xing Zhang

发明人： Ru Huang ,  Min Li ,  Xia An ,  Ming Li ,  Meng Lin ,  Xing Zhang

IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  C25F3/00

CPC分类号： H01L21/02052 ,  H01L21/306

摘要： Disclosed herein is an interface treatment method for germanium-based device, which belongs to the field of manufacturing technologies of ultra large scaled integrated (ULSI) circuits. In the method, the natural oxide layer on the surface of the germanium-based substrate is removed by using a concentrated hydrochloric acid solution having a mass percentage concentration of 15%˜36%, and dangling bonds of the surface are performed a passivation treatment by using a diluted hydrochloric acid solution having a mass percentage concentration of 5%˜10% so as to form a stable passivation layer on the surface. This method makes a good foundation for depositing a high-K (high dielectric constant) gate dielectric on the surface of the germanium-based substrate after cleaning and passivating, enhances quality of the interface between the gate dielectric and the substrate, and improves the electrical performance of germanium-based MOS device.

摘要翻译： 本文公开了一种锗系器件的接口处理方法，属于超大规模集成（ULSI）电路制造技术领域。 在该方法中，通过使用质量百分比浓度为15％〜36％的浓盐酸溶液除去锗系基板表面上的天然氧化物层，并且通过使表面的悬空键进行钝化处理 使用质量百分比浓度为5％〜10％的稀盐酸溶液，以在表面上形成稳定的钝化层。 该方法为清洗和钝化后在锗基基板表面上沉积高K（高介电常数）栅极电介质提供了良好的基础，提高了栅极电介质和基板之间界面的质量，改善了电气 锗系MOS器件的性能。

公开(公告)号：US20130309875A1

公开(公告)日：2013-11-21

申请号：US13702562

申请日：2012-06-14

申请人： Ru Huang ,  Min Li ,  Xia An ,  Ming Li ,  Meng Lin ,  Xing Zhang

发明人： Ru Huang ,  Min Li ,  Xia An ,  Ming Li ,  Meng Lin ,  Xing Zhang

IPC分类号： H01L21/02

CPC分类号： H01L21/02052 ,  H01L21/306

摘要： Disclosed herein is an interface treatment method for germanium-based device, which belongs to the field of manufacturing technologies of ultra large scaled integrated (ULSI) circuits. In the method, the natural oxide layer on ther surface of the germanium-based substrate is removed by using a concentrated hydrochloric acid solution having a mass percentage concentration of 15%˜36%, and dangling bonds of the surface are performed a passivation treatment by using a diluted hydrochloric acid solution having a mass percentage concentration of 5%˜10% so as to form a stable passivation layer on the surface. This method makes a good foundation for depositing a high-K (high dielectric constant) gate dielectric on the surface of the germanium-based substrate after cleaning and passivating, enhances quality of the interface between the gate dielectric and the substrate, and improves the electrical performance of germanium-based MOS device.

摘要翻译： 本文公开了一种锗系器件的接口处理方法，属于超大规模集成（ULSI）电路制造技术领域。 在该方法中，通过使用质量百分比浓度为15％〜36％的浓盐酸溶液除去锗基底板的表面上的天然氧化物层，并且通过以下方式进行钝化处理： 使用质量百分比浓度为5％〜10％的稀盐酸溶液，以在表面上形成稳定的钝化层。 该方法为清洗和钝化后在锗基基板表面上沉积高K（高介电常数）栅极电介质提供了良好的基础，提高了栅极电介质和基板之间界面的质量，改善了电气 锗系MOS器件的性能。

公开(公告)号：US09147597B2

公开(公告)日：2015-09-29

申请号：US14344050

申请日：2012-06-14

申请人： Ming Li ,  Min Li ,  Ru Huang ,  Xia An ,  Xing Zhang

发明人： Ming Li ,  Min Li ,  Ru Huang ,  Xia An ,  Xing Zhang

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/76232 ,  H01L21/02052 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/28255 ,  H01L21/32 ,  H01L21/7621 ,  H01L21/763

摘要： Disclosed herein is a method for isolating active regions in a germanium-based MOS device. A surface of a germanium-based substrate is covered by a thin polysilicon layer or a poly-SiGe layer, and an isolation structure of germanium dioxide covered by a silicon dioxide layer or a SiGe oxide layer on top is formed by means of two steps of oxidation in a case of the active regions are protected. Such two steps of oxidation using the polysilicon layer or the poly-SiGe layer as a sacrificial layer is advantageous to improve the isolation quality of a fabricated germanium dioxide and to reduce a beak effect occurred during a local field oxygen oxidation so as to dramatically elevate the performance of the germanium device.

摘要翻译： 本文公开了一种用于隔离锗基MOS器件中的有源区的方法。 基于锗的衬底的表面被薄的多晶硅层或多晶硅层覆盖，并且通过两个步骤形成由二氧化硅层或顶部的SiGe氧化物层覆盖的二氧化锗的隔离结构 在活性区域的情况下的氧化被保护。 使用多晶硅层或多晶硅层作为牺牲层的这两个氧化步骤有利于提高制造的二氧化锗的隔离质量，并且减少在局部场氧氧化期间发生的喙效应，从而显着提升 锗器件的性能。

公开(公告)号：US20150031188A1

公开(公告)日：2015-01-29

申请号：US14344050

申请日：2012-06-14

申请人： Ming Li ,  Min Li ,  Ru Huang ,  Xia An ,  Xing Zhang

发明人： Ming Li ,  Min Li ,  Ru Huang ,  Xia An ,  Xing Zhang

IPC分类号： H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/02052 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/28255 ,  H01L21/32 ,  H01L21/7621 ,  H01L21/763

摘要： Disclosed herein is a method for isolating active regions in a germanium-based MOS device. A surface of a germanium-based substrate is covered by a thin polysilicon layer or a poly-SiGe layer, and an isolation structure of germanium dioxide covered by a silicon dioxide layer or a SiGe oxide layer on top is formed by means of two steps of oxidation in a case of the active regions are protected. Such two steps of oxidation using the polysilicon layer or the poly-SiGe layer as a sacrificial layer is advantageous to improve the isolation quality of a fabricated germanium dioxide and to reduce a beak effect occurred during a local field oxygen oxidation so as to dramatically elevate the performance of the germanium device.

摘要翻译： 本文公开了一种用于隔离锗基MOS器件中的有源区的方法。 基于锗的衬底的表面被薄的多晶硅层或多晶硅层覆盖，并且通过两个步骤形成由二氧化硅层或顶部的SiGe氧化物层覆盖的二氧化锗的隔离结构 在活性区域的情况下的氧化被保护。 使用多晶硅层或多晶硅层作为牺牲层的这两个氧化步骤有利于提高制造的二氧化锗的隔离质量，并且减少在局部场氧氧化期间发生的喙效应，从而显着提升 锗器件的性能。

公开(公告)号：US08450155B2

公开(公告)日：2013-05-28

申请号：US13131602

申请日：2011-04-01

申请人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Xing Zhang

发明人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Xing Zhang

IPC分类号： H01L21/332 ,  H01L21/335 ,  H01L21/8232 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7848 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

摘要： The present invention relates to CMOS ultra large scale integrated circuits, and provides a method for introducing channel stress and a field effect transistor fabricated by the same. According to the present invention, a strained dielectric layer is interposed between source/drain regions and a substrate of a field effect transistor, and a strain is induced in a channel by the strained dielectric layer which directly contacts the substrate, so as to improve a carrier mobility of the channel and a performance of the device. The specific effects of the invention include: a tensile strain may be induced in the channel by using the strained dielectric layer having a tensile strain in order to increase an electron mobility of the channel; a compressive strain may be induced in the channel by using the strained dielectric layer having a compressive strain in order to increase a hole mobility of the channel. According to the invention, not only an effectiveness of the introduction of channel stress is ensued, but the device structure of the field effect transistor is also improved fundamentally, so that a capability for suppressing a short channel effect of the device is increased.

摘要翻译： 本发明涉及CMOS超大规模集成电路，并且提供了一种引入沟道应力的方法和由其制造的场效应晶体管。 根据本发明，应变电介质层介于源极/漏极区域和场效应晶体管的衬底之间，并且通过直接接触衬底的应变介电层在沟道中诱发应变，从而改善 信道的载波移动性和设备的性能。 本发明的具体效果包括：通过使用具有拉伸应变的应变电介质层，可以在沟道中诱发拉伸应变，以增加通道的电子迁移率; 可以通过使用具有压缩应变的应变电介质层在沟道中诱发压缩应变，以增加通道的空穴迁移率。 根据本发明，不仅引入通道应力的有效性，而且基本上也提高了场效应晶体管的器件结构，从而增加了抑制器件的短沟道效应的能力。

公开(公告)号：US20120187495A1

公开(公告)日：2012-07-26

申请号：US13201618

申请日：2010-09-25

申请人： Xia An ,  Yue Guo ,  Quanxin Yun ,  Ru Huang ,  Xing Zhang

发明人： Xia An ,  Yue Guo ,  Quanxin Yun ,  Ru Huang ,  Xing Zhang

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L29/16 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： The present invention provides a semiconductor device and a method for fabricating the same, wherein the method comprises: providing a germanium-based semiconductor substrate having a plurality of active regions and device isolation regions between the plurality of the active regions, wherein a gate dielectric layer and a gate over the gate dielectric layer are provided on the active regions, and the active regions include source and drain extension regions and deep source and drain regions; performing a first ion implantation process with respect to the source and drain extension regions, wherein the ions implanted in the first ion implantation process include silicon or carbon; performing a second ion implantation process with respect to the source and drain extension regions; performing a third ion implantation process with respect to the deep source and drain regions; performing an annealing process with respect to the germanium-based semiconductor substrate which has been subjected to the third ion implantation process. According to the method for fabricating a semiconductor device, through the implantation of silicon impurities, appropriate stress may be introduced into the germanium channel effectively by the mismatch of lattices in the source and drain regions, so that the mobility of electrons in the channel is enhanced and the performance of the device is improved.

摘要翻译： 本发明提供了一种半导体器件及其制造方法，其中该方法包括：在多个有源区之间提供具有多个有源区和器件隔离区的锗基半导体衬底，其中栅介电层 并且栅极电介质层上的栅极设置在有源区上，有源区包括源极和漏极延伸区以及深的源极和漏极区; 对源极和漏极延伸区域执行第一离子注入工艺，其中在第一离子注入工艺中注入的离子包括硅或碳; 对源极和漏极延伸区域执行第二离子注入工艺; 相对于深源极和漏极区域执行第三离子注入工艺; 对已进行第三离子注入工艺的锗基半导体衬底进行退火处理。 根据制造半导体器件的方法，通过硅杂质的注入，可以通过栅极和漏极区域中的晶格失配有效地将适当的应力引入锗通道中，使得沟道中电子的迁移率增强 并提高了设备​​的性能。

公开(公告)号：US08673722B2

公开(公告)日：2014-03-18

申请号：US13255443

申请日：2011-03-23

申请人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Yujie Al ,  Xing Zhang

发明人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Yujie Al ,  Xing Zhang

IPC分类号： H01L21/336

CPC分类号： H01L29/0653 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/7849

摘要： The present invention discloses a strained channel field effect transistor and a method for fabricating the same. The field effect transistor comprises a substrate, a source/drain, a gate dielectric layer, and a gate, characterized in that, an “L” shaped composite isolation layer, which envelops a part of a side face of the source/drain adjacent to a channel and the bottom of the source/drain, is arranged between the source/drain and the substrate; the composite isolation layer is divided into two layers, that is, an “L” shaped insulation thin layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source and the drain. The field effect transistor of such a structure improves the mobility of charge carriers by introducing stress into the channel by means of the high stress layer, while fundamentally improving the device structure of the field effect transistor and improving the short channel effect suppressing ability of the device.

摘要翻译： 本发明公开了一种应变通道场效应晶体管及其制造方法。 场效应晶体管包括衬底，源极/漏极，栅极电介质层和栅极，其特征在于，“L”形复合隔离层，其包围与源极/漏极相邻的侧面的一部分 沟道和源极/漏极的底部布置在源极/漏极和衬底之间; 复合隔离层分为两层，即与基板直接接触的“L”形绝缘薄层和与源极和漏极直接接触的“L”形高应力层。 这种结构的场效应晶体管通过高应力层向沟道中引入应力而提高了载流子的迁移率，同时从根本上改善了场效应晶体管的器件结构，提高了器件的短沟道效应抑制能力 。

公开(公告)号：US20130161757A1

公开(公告)日：2013-06-27

申请号：US13582034

申请日：2012-04-16

申请人： Ru Huang ,  Fei Tan ,  Xia An ,  Qianqian Huang ,  Dong Yang ,  Xing Zhang

发明人： Ru Huang ,  Fei Tan ,  Xia An ,  Qianqian Huang ,  Dong Yang ,  Xing Zhang

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/02203 ,  H01L21/02216 ,  H01L21/3063 ,  H01L21/823878 ,  H01L27/0921

摘要： The present invention discloses a CMOS device of reducing charge sharing effect and a fabrication method thereof. The present invention has an additional isolation for trapping carriers disposed right below an isolation region. the material of the additional isolation region is porous silicon. Since porous silicon is a functional material of spongy structure by electrochemistry anodic oxidizing monocrystalline silicon wafer, there are a large number of microvoids and dangling bonds on the surface layer of the porous silicon. These defects may form defect states in a center of forbidden band of the porous silicon, the defect states may trap carriers so as to cause an increased resistance. And with an increase of density of corrosion current, porosity increases, and defects in the porous silicon increase. The present invention can reduce the charge sharing effect due to heavy ions by using a feature that the defect states in the porous silicon trap carriers, the formation of a shallow trench isolation (STI) region and a isolation region underneath only needs one time photolithography, and the process is simple, so that radioresistance performance of an integrated circuit may be greatly increased.

摘要翻译： 本发明公开了一种降低电荷共享效应的CMOS器件及其制造方法。 本发明对于设置在隔离区域正下方的捕获载体具有额外的隔离。 附加隔离区的材料是多孔硅。 由于多孔硅是通过电化学阳极氧化单晶硅晶片的海绵结构的功能材料，因此在多孔硅的表面层上存在大量微孔和悬挂键。 这些缺陷可能在多孔硅的禁带的中心形成缺陷状态，缺陷状态可能会捕获载体以引起增加的电阻。 随着腐蚀电流密度的增加，孔隙率增加，多孔硅中的缺陷增加。 本发明可以通过使用多孔硅捕集载体中的缺陷状态，浅沟槽隔离（STI）区域的形成和下面的隔离区域仅需要一次光刻来降低由于重离子引起的电荷共享效应， 并且该工艺简单，从而可以大大提高集成电路的射电阻性能。

公开(公告)号：US20130119445A1

公开(公告)日：2013-05-16

申请号：US13509170

申请日：2011-11-30

申请人： Ru Huang ,  Fei Tan ,  Xia An ,  Qianqian Huang ,  Dong Yang ,  Xing Zhang

发明人： Ru Huang ,  Fei Tan ,  Xia An ,  Qianqian Huang ,  Dong Yang ,  Xing Zhang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/6653 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

摘要： A CMOS device for reducing a radiation-induced charge collection and a method for fabricating the same. In the CMOS device, a heavily doped charge collection-suppressed region is disposed directly under the source region and the drain region. The region has a doping type opposite that of the source region and the drain region, and has a doping concentration not less than that of the source region and the drain region. The charge collection-suppressed region has a lateral part slightly less than or equal to that of the source region and the drain region, and has a lateral range toward to the channel not exceed the edges of the source region and the drain region. The CMOS device may greatly reduce a range of the funnel that appears under the action of a single particle, so that charges collected instantaneously under a force of an electric field may be reduced.

摘要翻译： 用于减少辐射诱导的电荷收集的CMOS器件及其制造方法。 在CMOS器件中，重掺杂电荷收集抑制区域直接设置在源极区域和漏极区域的正下方。 该区域具有与源极区域和漏极区域相反的掺杂类型，并且具有不小于源极区域和漏极区域的掺杂浓度。 电荷收集抑制区域具有稍小于或等于源极区域和漏极区域的横向部分，并且具有朝向沟道的横向范围不超过源极区域和漏极区域的边缘。 CMOS器件可以大大减少在单个粒子的作用下出现的漏斗的范围，使得可以在电场的力作用下立即收集的电荷减少。

公开(公告)号：US08865543B2

公开(公告)日：2014-10-21

申请号：US13580971

申请日：2012-02-21

申请人： Ru Huang ,  Zhiqiang Li ,  Xia An ,  Yue Guo ,  Xing Zhang

发明人： Ru Huang ,  Zhiqiang Li ,  Xia An ,  Yue Guo ,  Xing Zhang

IPC分类号： H01L21/8242 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51

CPC分类号： H01L29/66477 ,  H01L29/0895 ,  H01L29/16 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/66643 ,  H01L29/78

摘要： The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO2) and metal oxide are deposited between the source/drain region and the substrate. The present invention not only reduces the electron Schottky barrier height of metal/Ge contact, but also improves the current switching ratio of the Ge-based Schottky and therefore, it will improve the performance of the Ge-based Schottky NMOS transistor. In addition, the fabrication process is very easy and completely compatible with the silicon CMOS process. As compared with conventional fabrication method, the Ge-based NMOS device structure and the fabrication method in the present invention can easily and effectively improve the performance of the Ge-based Schottky NMOS transistor.

摘要翻译： 本发明的实施例提供了一种基于Ge的NMOS器件结构及其制造方法。 通过使用该方法，在源极/漏极区域和衬底之间沉积氧化锗（GeO 2）和金属氧化物的双电介质层。 本发明不仅降低了金属/ Ge接触的电子肖特基势垒高度，而且提高了基于Ge的肖特基的电流切换比，从而提高了Ge基肖特基NMOS晶体管的性能。 此外，制造工艺非常容易和完全兼容硅CMOS工艺。 与传统的制造方法相比，本发明中的Ge基NMOS器件结构和制造方法可以容易且有效地改善Ge基肖特基NMOS晶体管的性能。