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1.发明授权Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core 有权具有石墨芯的复合晶片的制造方法以及具有石墨芯的复合晶片公开(公告)号：US08822306B2
公开(公告)日：2014-09-02
申请号：US13206029
申请日：2011-08-09
申请人： Rudolf Berger , Hermann Gruber , Wolfgang Lehnert , Guenther Ruhl , Raimund Foerg , Anton Mauder , Hans-Joachim Schulze , Karsten Kellermann , Michael Sommer , Christian Rottmair , Roland Rupp
发明人： Rudolf Berger , Hermann Gruber , Wolfgang Lehnert , Guenther Ruhl , Raimund Foerg , Anton Mauder , Hans-Joachim Schulze , Karsten Kellermann , Michael Sommer , Christian Rottmair , Roland Rupp
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , C30B25/186 , H01L21/02115 , H01L21/02282 , H01L21/02598 , H01L21/2007 , H01L21/265 , H01L21/3212 , H01L21/324 , H01L21/76251 , H01L29/1608 , H01L29/20 , H01L29/2003
摘要： According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate.
摘要翻译： 根据实施例，复合晶片包括具有石墨层和附着到载体衬底的单晶半导体层的载体衬底。
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2.发明授权Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core 有权具有石墨芯的复合晶片的制造方法以及具有石墨芯的复合晶片公开(公告)号：US08404562B2
公开(公告)日：2013-03-26
申请号：US12894344
申请日：2010-09-30
申请人： Rudolf Berger , Hermann Gruber , Wolfgang Lehnert , Guenther Ruhl , Raimund Foerg , Anton Mauder , Hans-Joachim Schulze
发明人： Rudolf Berger , Hermann Gruber , Wolfgang Lehnert , Guenther Ruhl , Raimund Foerg , Anton Mauder , Hans-Joachim Schulze
IPC分类号： H01L21/322 , H01L21/00 , H01L21/31
CPC分类号： H01L21/76251 , H01L21/02002 , H01L21/0237 , H01L21/0243 , H01L21/02527 , H01L21/02601 , H01L21/02628 , H01L21/7624 , H01L29/02 , H01L29/04 , H01L29/16 , H01L29/1608 , H01L29/161
摘要： According to an embodiment, a composite wafer includes a carrier substrate having a graphite core and a monocrystalline semiconductor layer attached to the carrier substrate.
摘要翻译： 根据实施例，复合晶片包括具有石墨芯和附着到载体衬底的单晶半导体层的载体衬底。
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3.发明申请Method for Manufacturing a Composite Wafer Having a Graphite Core, and Composite Wafer Having a Graphite Core 有权制造具有石墨芯的复合晶片的方法和具有石墨芯的复合晶片公开(公告)号：US20120083098A1
公开(公告)日：2012-04-05
申请号：US13206029
申请日：2011-08-09
申请人： Rudolf Berger , Hermann Gruber , Wolfgang Lehnert , Guenther Ruhl , Raimund Foerg , Anton Mauder , Hans-Joachim Schulze , Karsten Kellermann , Michael Sommer , Christian Rottmair , Roland Rupp
发明人： Rudolf Berger , Hermann Gruber , Wolfgang Lehnert , Guenther Ruhl , Raimund Foerg , Anton Mauder , Hans-Joachim Schulze , Karsten Kellermann , Michael Sommer , Christian Rottmair , Roland Rupp
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , C30B25/186 , H01L21/02115 , H01L21/02282 , H01L21/02598 , H01L21/2007 , H01L21/265 , H01L21/3212 , H01L21/324 , H01L21/76251 , H01L29/1608 , H01L29/20 , H01L29/2003
摘要： According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate.
摘要翻译： 根据实施例，复合晶片包括具有石墨层和附着到载体衬底的单晶半导体层的载体衬底。
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4.发明申请Method for Manufacturing a Composite Wafer Having a Graphite Core, and Composite Wafer Having a Graphite Core 有权制造具有石墨芯的复合晶片的方法和具有石墨芯的复合晶片公开(公告)号：US20120080690A1
公开(公告)日：2012-04-05
申请号：US12894344
申请日：2010-09-30
申请人： Rudolf Berger , Hermann Gruber , Wolfgang Lehnert , Guenther Ruhl , Raimund Foerg , Anton Mauder , Hans-Joachim Schulze
发明人： Rudolf Berger , Hermann Gruber , Wolfgang Lehnert , Guenther Ruhl , Raimund Foerg , Anton Mauder , Hans-Joachim Schulze
CPC分类号： H01L21/76251 , H01L21/02002 , H01L21/0237 , H01L21/0243 , H01L21/02527 , H01L21/02601 , H01L21/02628 , H01L21/7624 , H01L29/02 , H01L29/04 , H01L29/16 , H01L29/1608 , H01L29/161
摘要： According to an embodiment, a composite wafer includes a carrier substrate having a graphite core and a monocrystalline semiconductor layer attached to the carrier substrate.
摘要翻译： 根据实施例，复合晶片包括具有石墨芯和附着到载体衬底的单晶半导体层的载体衬底。
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5.发明授权公开(公告)号：US08786012B2
公开(公告)日：2014-07-22
申请号：US13542737
申请日：2012-07-06
申请人： Anton Mauder , Franz Hirler , Wolfgang Lehnert , Rudolf Berger , Klemens Pruegl , Hans-Joachim Schulze , Helmut Strack
发明人： Anton Mauder , Franz Hirler , Wolfgang Lehnert , Rudolf Berger , Klemens Pruegl , Hans-Joachim Schulze , Helmut Strack
IPC分类号： H01L29/66
CPC分类号： H01L21/28194 , H01L21/02109 , H01L21/02145 , H01L21/0228 , H01L29/0653 , H01L29/0878 , H01L29/1608 , H01L29/2003 , H01L29/402 , H01L29/407 , H01L29/408 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/51 , H01L29/513 , H01L29/66734 , H01L29/7393 , H01L29/7394 , H01L29/7397 , H01L29/7803 , H01L29/7811 , H01L29/7813 , H01L29/7835 , H01L29/792 , H01L29/8611
摘要： A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.
摘要翻译： 功率半导体器件具有半导体本体，该半导体本体包括有源区域和限定半导体本体的水平主表面的周边区域。 半导体本体还包括n型半导体层，pn结和至少一个沟槽。 n型半导体层嵌入半导体本体中并延伸到周边区域的主表面。 pn结布置在有源区域中的n型半导体层和主表面之间。 至少一个沟槽在外围区域中从主表面延伸到n型半导体层中，并且包括具有固定的负电荷的电介质层。 在垂直方向上，介电层布置在pn结的下方和上方。 具有固定负电荷的电介质层通常具有负的净电荷。 此外，提供了一种用于形成半导体器件的方法。
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公开(公告)号：US08748974B2
公开(公告)日：2014-06-10
申请号：US13542737
申请日：2012-07-06
申请人： Anton Mauder , Franz Hirler , Wolfgang Lehnert , Rudolf Berger , Klemens Pruegl , Hans-Joachim Schulze , Helmut Strack
发明人： Anton Mauder , Franz Hirler , Wolfgang Lehnert , Rudolf Berger , Klemens Pruegl , Hans-Joachim Schulze , Helmut Strack
IPC分类号： H01L29/66
摘要： A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.
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7.发明申请公开(公告)号：US20120286355A1
公开(公告)日：2012-11-15
申请号：US13542737
申请日：2012-07-06
申请人： Anton Mauder , Franz Hirler , Wolfgang Lehnert , Rudolf Berger , Klemens Pruegl , Hans-Joachim Schulze , Helmut Strack
发明人： Anton Mauder , Franz Hirler , Wolfgang Lehnert , Rudolf Berger , Klemens Pruegl , Hans-Joachim Schulze , Helmut Strack
IPC分类号： H01L29/78 , H01L21/302 , H01L29/02
CPC分类号： H01L21/28194 , H01L21/02109 , H01L21/02145 , H01L21/0228 , H01L29/0653 , H01L29/0878 , H01L29/1608 , H01L29/2003 , H01L29/402 , H01L29/407 , H01L29/408 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/51 , H01L29/513 , H01L29/66734 , H01L29/7393 , H01L29/7394 , H01L29/7397 , H01L29/7803 , H01L29/7811 , H01L29/7813 , H01L29/7835 , H01L29/792 , H01L29/8611
摘要： A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.
摘要翻译： 功率半导体器件具有半导体本体，该半导体本体包括有源区域和限定半导体本体的水平主表面的周边区域。 半导体本体还包括n型半导体层，pn结和至少一个沟槽。 n型半导体层嵌入半导体本体中并延伸到周边区域的主表面。 pn结布置在有源区域中的n型半导体层和主表面之间。 至少一个沟槽在外围区域中从主表面延伸到n型半导体层中，并且包括具有固定的负电荷的电介质层。 在垂直方向上，介电层布置在pn结的下方和上方。 具有固定负电荷的电介质层通常具有负的净电荷。 此外，提供了一种用于形成半导体器件的方法。
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公开(公告)号：US20120217580A1
公开(公告)日：2012-08-30
申请号：US13463243
申请日：2012-05-03
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66719 , H01L29/0878 , H01L29/407 , H01L29/408 , H01L29/42368 , H01L29/513 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.
摘要翻译： 半导体器件包括源极，漏极和被配置为选择性地使电流在源极和漏极之间通过的栅极。 半导体器件包括源极和漏极之间的漂移区和邻近漂移区的第一场板。 半导体器件包括将第一场板与漂移区电隔离的电介质层，并且电介质层内的电荷接近靠近漂移区的电介质层的界面。
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公开(公告)号：US08502315B2
公开(公告)日：2013-08-06
申请号：US13463243
申请日：2012-05-03
IPC分类号： H01L29/78
CPC分类号： H01L29/66719 , H01L29/0878 , H01L29/407 , H01L29/408 , H01L29/42368 , H01L29/513 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.
摘要翻译： 半导体器件包括源极，漏极和被配置为选择性地使电流在源极和漏极之间通过的栅极。 半导体器件包括源极和漏极之间的漂移区和邻近漂移区的第一场板。 半导体器件包括将第一场板与漂移区电隔离的电介质层，并且电介质层内的电荷接近靠近漂移区的电介质层的界面。
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公开(公告)号：US08198678B2
公开(公告)日：2012-06-12
申请号：US12633956
申请日：2009-12-09
IPC分类号： H01L29/78
CPC分类号： H01L29/66719 , H01L29/0878 , H01L29/407 , H01L29/408 , H01L29/42368 , H01L29/513 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.
摘要翻译： 半导体器件包括源极，漏极和被配置为选择性地使电流在源极和漏极之间通过的栅极。 半导体器件包括源极和漏极之间的漂移区和邻近漂移区的第一场板。 半导体器件包括将第一场板与漂移区电隔离的电介质层，并且电介质层内的电荷接近靠近漂移区的电介质层的界面。
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