公开(公告)号：US20120083098A1

公开(公告)日：2012-04-05

申请号：US13206029

申请日：2011-08-09

申请人： Rudolf Berger ,  Hermann Gruber ,  Wolfgang Lehnert ,  Guenther Ruhl ,  Raimund Foerg ,  Anton Mauder ,  Hans-Joachim Schulze ,  Karsten Kellermann ,  Michael Sommer ,  Christian Rottmair ,  Roland Rupp

发明人： Rudolf Berger ,  Hermann Gruber ,  Wolfgang Lehnert ,  Guenther Ruhl ,  Raimund Foerg ,  Anton Mauder ,  Hans-Joachim Schulze ,  Karsten Kellermann ,  Michael Sommer ,  Christian Rottmair ,  Roland Rupp

IPC分类号： H01L21/30

CPC分类号： H01L21/76254 ,  C30B25/186 ,  H01L21/02115 ,  H01L21/02282 ,  H01L21/02598 ,  H01L21/2007 ,  H01L21/265 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/76251 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003

摘要： According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate.

摘要翻译： 根据实施例，复合晶片包括具有石墨层和附着到载体衬底的单晶半导体层的载体衬底。

公开(公告)号：US08822306B2

公开(公告)日：2014-09-02

申请号：US13206029

申请日：2011-08-09

申请人： Rudolf Berger ,  Hermann Gruber ,  Wolfgang Lehnert ,  Guenther Ruhl ,  Raimund Foerg ,  Anton Mauder ,  Hans-Joachim Schulze ,  Karsten Kellermann ,  Michael Sommer ,  Christian Rottmair ,  Roland Rupp

发明人： Rudolf Berger ,  Hermann Gruber ,  Wolfgang Lehnert ,  Guenther Ruhl ,  Raimund Foerg ,  Anton Mauder ,  Hans-Joachim Schulze ,  Karsten Kellermann ,  Michael Sommer ,  Christian Rottmair ,  Roland Rupp

IPC分类号： H01L21/30

CPC分类号： H01L21/76254 ,  C30B25/186 ,  H01L21/02115 ,  H01L21/02282 ,  H01L21/02598 ,  H01L21/2007 ,  H01L21/265 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/76251 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003

摘要： According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate.

摘要翻译： 根据实施例，复合晶片包括具有石墨层和附着到载体衬底的单晶半导体层的载体衬底。

公开(公告)号：US08404562B2

公开(公告)日：2013-03-26

申请号：US12894344

申请日：2010-09-30

申请人： Rudolf Berger ,  Hermann Gruber ,  Wolfgang Lehnert ,  Guenther Ruhl ,  Raimund Foerg ,  Anton Mauder ,  Hans-Joachim Schulze

发明人： Rudolf Berger ,  Hermann Gruber ,  Wolfgang Lehnert ,  Guenther Ruhl ,  Raimund Foerg ,  Anton Mauder ,  Hans-Joachim Schulze

IPC分类号： H01L21/322 ,  H01L21/00 ,  H01L21/31

CPC分类号： H01L21/76251 ,  H01L21/02002 ,  H01L21/0237 ,  H01L21/0243 ,  H01L21/02527 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/7624 ,  H01L29/02 ,  H01L29/04 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161

摘要： According to an embodiment, a composite wafer includes a carrier substrate having a graphite core and a monocrystalline semiconductor layer attached to the carrier substrate.

摘要翻译： 根据实施例，复合晶片包括具有石墨芯和附着到载体衬底的单晶半导体层的载体衬底。

公开(公告)号：US20120080690A1

公开(公告)日：2012-04-05

申请号：US12894344

申请日：2010-09-30

申请人： Rudolf Berger ,  Hermann Gruber ,  Wolfgang Lehnert ,  Guenther Ruhl ,  Raimund Foerg ,  Anton Mauder ,  Hans-Joachim Schulze

发明人： Rudolf Berger ,  Hermann Gruber ,  Wolfgang Lehnert ,  Guenther Ruhl ,  Raimund Foerg ,  Anton Mauder ,  Hans-Joachim Schulze

IPC分类号： H01L29/24 ,  H01L21/30 ,  H01L29/02 ,  H01L21/20

CPC分类号： H01L21/76251 ,  H01L21/02002 ,  H01L21/0237 ,  H01L21/0243 ,  H01L21/02527 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/7624 ,  H01L29/02 ,  H01L29/04 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161

摘要： According to an embodiment, a composite wafer includes a carrier substrate having a graphite core and a monocrystalline semiconductor layer attached to the carrier substrate.

摘要翻译： 根据实施例，复合晶片包括具有石墨芯和附着到载体衬底的单晶半导体层的载体衬底。

公开(公告)号：US07947569B2

公开(公告)日：2011-05-24

申请号：US12164652

申请日：2008-06-30

申请人： Anton Mauder ,  Frank Pfirsch ,  Rudolf Berger ,  Stefan Sedlmaier ,  Wolfgang Lehnert ,  Raimund Foerg

发明人： Anton Mauder ,  Frank Pfirsch ,  Rudolf Berger ,  Stefan Sedlmaier ,  Wolfgang Lehnert ,  Raimund Foerg

IPC分类号： H01L21/76

CPC分类号： H01L29/7813 ,  H01L21/8249 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7804

摘要： A method for producing a semiconductor including a material layer. In one embodiment a trench is produced having two opposite sidewalls and a bottom, in a semiconductor body. A foreign material layer is produced on a first one of the two sidewalls of the trench. The trench is filled by epitaxially depositing a semiconductor material onto the second one of the two sidewalls and the bottom of the trench.

摘要翻译： 一种用于制造包括材料层的半导体的方法。 在一个实施例中，在半导体本体中产生具有两个相对的侧壁和底部的沟槽。 在沟槽的两个侧壁的第一个上产生异物层。 通过将半导体材料外延地沉积到沟槽的两个侧壁和沟槽的底部中的第二个上来填充沟槽。

公开(公告)号：US20090325361A1

公开(公告)日：2009-12-31

申请号：US12164652

申请日：2008-06-30

申请人： Anton Mauder ,  Frank Pfirsch ,  Rudolf Berger ,  Stefan Sedlmaier ,  Wolfgang Lehnert ,  Raimund Foerg

发明人： Anton Mauder ,  Frank Pfirsch ,  Rudolf Berger ,  Stefan Sedlmaier ,  Wolfgang Lehnert ,  Raimund Foerg

IPC分类号： H01L21/762

CPC分类号： H01L29/7813 ,  H01L21/8249 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7804

摘要： A method for producing a semiconductor including a material layer. In one embodiment a trench is produced having two opposite sidewalls and a bottom, in a semiconductor body. A foreign material layer is produced on a first one of the two sidewalls of the trench. The trench is filled by epitaxially depositing a semiconductor material onto the second one of the two sidewalls and the bottom of the trench.

摘要翻译： 一种用于制造包括材料层的半导体的方法。 在一个实施例中，在半导体本体中产生具有两个相对的侧壁和底部的沟槽。 在沟槽的两个侧壁的第一个上产生异物层。 通过将半导体材料外延地沉积到沟槽的两个侧壁和沟槽的底部中的第二个上来填充沟槽。

公开(公告)号：US08786012B2

公开(公告)日：2014-07-22

申请号：US13542737

申请日：2012-07-06

申请人： Anton Mauder ,  Franz Hirler ,  Wolfgang Lehnert ,  Rudolf Berger ,  Klemens Pruegl ,  Hans-Joachim Schulze ,  Helmut Strack

发明人： Anton Mauder ,  Franz Hirler ,  Wolfgang Lehnert ,  Rudolf Berger ,  Klemens Pruegl ,  Hans-Joachim Schulze ,  Helmut Strack

IPC分类号： H01L29/66

CPC分类号： H01L21/28194 ,  H01L21/02109 ,  H01L21/02145 ,  H01L21/0228 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66734 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7835 ,  H01L29/792 ,  H01L29/8611

摘要： A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.

摘要翻译： 功率半导体器件具有半导体本体，该半导体本体包括有源区域和限定半导体本体的水平主表面的周边区域。 半导体本体还包括n型半导体层，pn结和至少一个沟槽。 n型半导体层嵌入半导体本体中并延伸到周边区域的主表面。 pn结布置在有源区域中的n型半导体层和主表面之间。 至少一个沟槽在外围区域中从主表面延伸到n型半导体层中，并且包括具有固定的负电荷的电介质层。 在垂直方向上，介电层布置在pn结的下方和上方。 具有固定负电荷的电介质层通常具有负的净电荷。 此外，提供了一种用于形成半导体器件的方法。

公开(公告)号：US08748974B2

公开(公告)日：2014-06-10

申请号：US13542737

申请日：2012-07-06

申请人： Anton Mauder ,  Franz Hirler ,  Wolfgang Lehnert ,  Rudolf Berger ,  Klemens Pruegl ,  Hans-Joachim Schulze ,  Helmut Strack

发明人： Anton Mauder ,  Franz Hirler ,  Wolfgang Lehnert ,  Rudolf Berger ,  Klemens Pruegl ,  Hans-Joachim Schulze ,  Helmut Strack

IPC分类号： H01L29/66

摘要： A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.

公开(公告)号：US20120286355A1

公开(公告)日：2012-11-15

申请号：US13542737

申请日：2012-07-06

申请人： Anton Mauder ,  Franz Hirler ,  Wolfgang Lehnert ,  Rudolf Berger ,  Klemens Pruegl ,  Hans-Joachim Schulze ,  Helmut Strack

发明人： Anton Mauder ,  Franz Hirler ,  Wolfgang Lehnert ,  Rudolf Berger ,  Klemens Pruegl ,  Hans-Joachim Schulze ,  Helmut Strack

IPC分类号： H01L29/78 ,  H01L21/302 ,  H01L29/02

CPC分类号： H01L21/28194 ,  H01L21/02109 ,  H01L21/02145 ,  H01L21/0228 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66734 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7835 ,  H01L29/792 ,  H01L29/8611

摘要： A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.

摘要翻译： 功率半导体器件具有半导体本体，该半导体本体包括有源区域和限定半导体本体的水平主表面的周边区域。 半导体本体还包括n型半导体层，pn结和至少一个沟槽。 n型半导体层嵌入半导体本体中并延伸到周边区域的主表面。 pn结布置在有源区域中的n型半导体层和主表面之间。 至少一个沟槽在外围区域中从主表面延伸到n型半导体层中，并且包括具有固定的负电荷的电介质层。 在垂直方向上，介电层布置在pn结的下方和上方。 具有固定负电荷的电介质层通常具有负的净电荷。 此外，提供了一种用于形成半导体器件的方法。

公开(公告)号：US20070108513A1

公开(公告)日：2007-05-17

申请号：US11540922

申请日：2006-09-29

申请人： Michael Rub ,  Herbert Schafer ,  Armin Willmeroth ,  Anton Mauder ,  Stefan Sedlmaier ,  Roland Rupp ,  Manfred Pippan ,  Hans Weber ,  Frank Pfirsch ,  Franz Hirler ,  Hans-Joachim Schulze

发明人： Michael Rub ,  Herbert Schafer ,  Armin Willmeroth ,  Anton Mauder ,  Stefan Sedlmaier ,  Roland Rupp ,  Manfred Pippan ,  Hans Weber ,  Frank Pfirsch ,  Franz Hirler ,  Hans-Joachim Schulze

IPC分类号： H01L31/00

CPC分类号： H01L29/7813 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7849

摘要： The fabrication of a semiconductor component having a semiconductor body in which is arranged a very thin dielectric layer having sections which run in the vertical direction and which extend very deeply into the semiconductor body is disclosed. In one method a trench is formed in a drift zone region proceeding from the front side of a semiconductor body, a sacrificial layer is produced on at least a portion of the sidewalls of the trench and at least a portion of the trench is filled with a semiconductor material which is chosen such that the quotient of the net dopant charge of the semiconductor material in the trench and the total area of the sacrificial layer on the sidewalls of the trench between the semiconductor material and the drift zone region is less than the breakdown charge of the semiconductor material, and the sacrificial layer is replaced with a dielectric.

摘要翻译： 公开了具有半导体主体的半导体部件的制造，其中布置有具有在垂直方向上延伸并且非常深地延伸到半导体本体中的截面的非常薄的电介质层。 在一种方法中，在从半导体主体的前侧开始的漂移区域中形成沟槽，在沟槽的至少一部分侧壁上产生牺牲层，并且沟槽的至少一部分填充有 半导体材料被选择为使得沟槽中的半导体材料的净掺杂剂电荷的商和半导体材料和漂移区域之间的沟槽的侧壁上的牺牲层的总面积小于击穿电荷 的半导体材料，并且牺牲层被电介质代替。