Semiconductor device with multi-layered electrodes
    1.
    发明授权
    Semiconductor device with multi-layered electrodes 失效
    具有多层电极的半导体器件

    公开(公告)号:US4451841A

    公开(公告)日:1984-05-29

    申请号:US225268

    申请日:1981-01-15

    摘要: A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an inter-layer insulating layer for insulating the first electrode is formed on the first electrode, and a first penetrating opening is provided in a part of the inter-layer insulating layer.Subsequently, a step of forming a second semiconductor circuit element is carried out, this step including a step of forming a second electrode so that at least a part thereof may overlie the inter-layer insulating layer at an area other than the first penetrating opening. Further, a subsidiary interconnection conductive layer is buried into the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third penetrating openings are respectively provided in the insulating layer over the second electrode and the interconnection subsidiary conductive layer.First and second interconnection conductors are respectively buried into the second and third penetrating openings. The first electrode is conductively connected with the second interconnection conductor in the third opening via the subsidiary interconnection conductive layer in the first opening. The second electrode is conductively connected with the first interconnection conductor in the second opening.

    摘要翻译: 包括第一电极的第一半导体电路元件形成在半导体衬底上,在第一电极上形成用于绝缘第一电极的层间绝缘层,并且第一穿透开口设置在层间绝缘体的一部分中 层。 随后,执行形成第二半导体电路元件的步骤,该步骤包括形成第二电极的步骤,使得其至少一部分可以覆盖除了第一穿透开口之外的区域的层间绝缘层。 此外,辅助互连导电层被埋入第一开口中。 在由此形成的结构上形成另一绝缘层,由此在第二电极和互连副导电层上的绝缘层中分别设置第二和第三穿透开口。 第一和第二互连导体分别埋入第二和第三穿透开口中。 第一电极通过第一开口中的辅助互连导电层与第三开口中的第二互连导体导电连接。 第二电极与第二开口中的第一互连导体导电连接。

    Process for making a memory device
    2.
    发明授权
    Process for making a memory device 失效
    制作存储设备的过程

    公开(公告)号:US4361949A

    公开(公告)日:1982-12-07

    申请号:US269507

    申请日:1981-06-01

    摘要: A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an insulating layer for insulating the first electrode is formed on the first electrode, and a first opening is provided in a part of this insulating layer.Subsequently, a second semiconductor circuit element is formed by forming a second electrode overlaying in part the insulating layer at an area other than the first opening and, a subsidiary conductive layer is formed in the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third openings are respectively provided in this latter insulating layer.First and second conductors are respectively deposited in the second and third openings, whereby electrical contact to the first and second electrodes are provided, with contact to the first electrode being via the subsidiary conductive layer.

    摘要翻译: 包括第一电极的第一半导体电路元件形成在半导体衬底上,在第一电极上形成用于绝缘第一电极的绝缘层,并且在该绝缘层的一部分中设置第一开口。 随后,通过形成第二电极形成第二半导体电路元件,该第二电极部分地覆盖除了第一开口之外的区域的绝缘层,并且在第一开口中形成辅助导电层。 在由此形成的结构上形成另一绝缘层,于是在后一绝缘层中分别设置第二和第三开口。 第一和第二导体分别沉积在第二和第三开口中,由此提供与第一和第二电极的电接触,与第一电极的接触经由辅助导电层。

    Semiconductor device and process for making the same
    3.
    发明授权
    Semiconductor device and process for making the same 失效
    半导体器件及其制造方法

    公开(公告)号:US4270262A

    公开(公告)日:1981-06-02

    申请号:US880618

    申请日:1978-02-23

    摘要: A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an inter-layer insulating layer for insulating the first electrode is formed on the first electrode, and a first penetrating opening is provided in a part of the inter-layer insulating layer.Subsequently, a step of forming a second semiconductor circuit element is carried out, this step including a step of forming a second electrode so that at least a part thereof may overlie the inter-layer insulating layer at an area other than the first penetrating opening. Further, a subsidiary interconnection conductive layer is buried into the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third penetrating openings are respectively provided in the insulating layer over the second electrode and the interconnection subsidiary conductive layer.First and second interconnection conductors are respectively buried into the second and third penetrating openings. The first electrode is conductively connected with the second interconnection conductor in the third opening via the subsidiary interconnection conductive layer in the first opening. The second electrode is conductively connected with the first interconnection conductor in the second opening.

    摘要翻译: 包括第一电极的第一半导体电路元件形成在半导体衬底上,在第一电极上形成用于绝缘第一电极的层间绝缘层,并且第一穿透开口设置在层间绝缘体的一部分中 层。 随后,执行形成第二半导体电路元件的步骤,该步骤包括形成第二电极的步骤,使得其至少一部分可以覆盖除了第一穿透开口之外的区域的层间绝缘层。 此外,辅助互连导电层被埋入第一开口中。 在由此形成的结构上形成另一绝缘层,由此在第二电极和互连副导电层上的绝缘层中分别设置第二和第三穿透开口。 第一和第二互连导体分别埋入第二和第三穿透开口中。 第一电极通过第一开口中的辅助互连导电层与第三开口中的第二互连导体导电连接。 第二电极与第二开口中的第一互连导体导电连接。

    MIS-FETs isolated on common substrate
    4.
    发明授权
    MIS-FETs isolated on common substrate 失效
    在公共基板上隔离的MIS-FET

    公开(公告)号:US4015281A

    公开(公告)日:1977-03-29

    申请号:US121375

    申请日:1971-03-05

    摘要: An enhancement-type and a depletion-type metal-insulator-semiconductor field effect transistor are formed on a common substrate of silicon and are electrically isolated from each other by a plurality of layers including, for example, a first layer of SiO.sub.2, a second layer of Al.sub.2 O.sub.3 capable of inducing holes in the surface portion of the substrate, and a third layer of SiO.sub.2, and the relation between the thicknesses of these layers is suitably selected for attaining the satisfactory isolation between these transistors.

    摘要翻译: 增强型和耗尽型金属 - 绝缘体 - 半导体场效应晶体管形成在公共的硅衬底上,并且通过多个层彼此电隔离,所述多个层包括例如第一SiO 2层,第二层 能够在衬底的表面部分中引入空穴的Al 2 O 3层和SiO 3层,并且适当地选择这些层的厚度之间的关系以获得这些晶体管之间的令人满意的隔离。

    Method for adjusting meshing position of hypoid gear
    5.
    发明授权
    Method for adjusting meshing position of hypoid gear 有权
    调整准双曲面齿轮啮合位置的方法

    公开(公告)号:US08813595B2

    公开(公告)日:2014-08-26

    申请号:US12742824

    申请日:2008-11-12

    摘要: A method for adjusting the meshing position of a hypoid gear having a first gear, and a second gear meshing with the first gear and transmitting the rotary motion thereof in the direction different from the extending direction of the axis of rotation of the first gear. The method for adjusting the meshing position comprises; a) a step for displacing the second gear a plurality of times along the axial direction of rotation while meshing with the first gear, b) a step for measuring the transmission error at each displacement position and plotting the relation of the displacement distance of the second gear and the measured transmission error, c) a step for evaluating the virtual transmission error between the measured transmission errors from the measured transmission error, d) a step for subtracting the measured transmission error and the virtual transmission error from a maximum allowable transmission error to determine the difference, e) a step for determining the area of a part surrounded by the difference and the maximum allowable transmission error by integrating the difference with the displacement distance of the second gear, and f) a step for dividing the part at a predetermined area ratio and setting a point where the division line intersects the displacement distance of the second gear at the meshing position of the second gear.

    摘要翻译: 一种用于调节具有第一齿轮的准双曲面齿轮的啮合位置的方法和与第一齿轮啮合的第二齿轮,并且沿与第一齿轮的旋转轴线的延伸方向不同的方向传递其旋转运动。 调整啮合位置的方法包括: a)在与所述第一齿轮啮合的同时使所述第二齿轮沿着轴向旋转多次的步骤,b)用于测量每个位移位置处的传动误差的步骤,并且绘制所述第二齿轮的位移距离的关系 齿轮和所测量的传输误差,c)根据测量的传输误差来评估所测量的传输误差之间的虚拟传输误差的步骤,d)从最大允许传输误差减去测量的传输误差和虚拟传输误差的步骤, 确定所述差异; e)通过将所述差与所述第二档位移距离进行积分来确定由所述差包围的部分的面积和所述最大允许传播误差的步骤,以及f)用于将所述部分划分为预定的步骤 并设定分割线与第二档位于距离的位移距离相交的点 第二档的铰接位置。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号:US4355374A

    公开(公告)日:1982-10-19

    申请号:US172378

    申请日:1980-07-24

    摘要: A semiconductor memory comprising a memory cell disposed on a p-type semiconductor substrate and including an insulated-gate field effect transistor and a storage capacitor. The storage capacitor comprises: an insulator capacitor including a first electrode disposed on the substrate, a film of Si.sub.3 N.sub.4 disposed on the first electrode, and a second electrode disposed on the Si.sub.3 N.sub.4 film; and a pn junction capacitor including a first n-type impurity region for constituting either the source or drain of the insulated-gate field effect transistor, and a second p-type impurity region disposed in contact with the first impurity region and having a higher impurity concentration than the substrate.

    摘要翻译: 一种半导体存储器,包括设置在p型半导体衬底上并包括绝缘栅场效应晶体管和存储电容器的存储单元。 存储电容器包括:绝缘体电容器,包括设置在基板上的第一电极,设置在第一电极上的Si 3 N 4膜和设置在Si 3 N 4膜上的第二电极; 以及包含用于构成绝缘栅场效应晶体管的源极或漏极的第一n型杂质区和与第一杂质区接触并具有较高杂质的第二p型杂质区的pn结电容器 浓度比底物。