公开(公告)号：US20210274646A1

公开(公告)日：2021-09-02

申请号：US16864741

申请日：2020-05-01

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Myeong Hui JUNG ,  Kwang Yun KIM

IPC: H05K1/02 ,  H05K1/11 ,  H01Q1/38

Abstract: The present disclosure relates to a printed circuit board and a module including the same. The printed circuit board includes an insulating body, a wiring pattern embedded in the insulating body, and a first conductor pattern disposed on the insulating body and overlapping at least a portion of the wiring pattern in a first direction. First conductive vias each penetrate a portion of the insulating body and are respectively disposed on opposite sides of the wiring pattern, in a second direction orthogonal to the first direction, to surround at least a portion of the wiring pattern. Each first conductive via has a first surface connected to the first conductor pattern, and a second surface, opposite to the first surface, connected to the insulating body.

公开(公告)号：US20230171895A1

公开(公告)日：2023-06-01

申请号：US17715266

申请日：2022-04-07

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kwang Yun KIM ,  Seung Eun LEE ,  Yong Hoon KIM

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H05K1/186 ,  H05K1/0298 ,  H01S5/183

Abstract: A printed circuit board (PCB) includes a substrate including a first insulating layer and first wiring patterns disposed on the first insulating layer, an optical sensing chip including a vertical cavity surface emitting laser (VCSEL) and a photodiode, disposed on the first insulating layer to be in contact with at least one of the first wiring patterns, a transimpedance amplifier (TIA) chip disposed to be spaced apart from the optical sensing chip on the first insulating layer and disposed to be in contact with at least one first wiring pattern, different from the first wiring pattern connected to the optical sensing chip, among the first wiring patterns, and a dielectric layer stacked on the substrate and having a hole exposing the VCSEL and the photodiode of the optical sensing chip. The optical sensing chip and the transimpedance amplifier chip are connected through a wiring pattern disposed on the dielectric layer.

公开(公告)号：US20240032202A1

公开(公告)日：2024-01-25

申请号：US18108846

申请日：2023-02-13

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kwang Yun KIM ,  Kyung Sang LIM ,  Seung Eun LEE ,  Yong Hoon KIM

IPC: H05K1/18 ,  G02B6/12 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/185 ,  G02B6/12004 ,  H05K1/0274 ,  H05K1/115 ,  H05K1/183 ,  H05K2201/10378 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10121

Abstract: A photonic integrated circuit embedded substrate may include: an embedded insulating layer on which a photonic integrated circuit is disposed, and at least one first insulating layer stacked on one surface of the embedded insulating layer. The at least one first insulating layer may have an optical path extending in a stacking direction of the at least one first insulating layer.

公开(公告)号：US20180350747A1

公开(公告)日：2018-12-06

申请号：US15713200

申请日：2017-09-22

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jun Oh HWANG ,  Kwang Yun KIM ,  Ki Jung SUNG

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L23/367 ,  H01L23/552

CPC classification number: H01L23/5386 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/18 ,  H01L2224/2401 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/24265 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2924/19102 ,  H01L2924/19105 ,  H01L2924/301 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/37001

Abstract: There is provided a fan-out semiconductor device in which a first package having a semiconductor chip disposed therein and having a fan-out form and a second package having a passive component disposed therein and having a fan-out form are stacked in a vertical direction so that the semiconductor chip and the passive component are electrically connected to each other by a path as short as possible.