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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220069011A1

    公开(公告)日：2022-03-03

    申请号：US17209660

    申请日：2021-03-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongho AHN ,  Segab KWON ,  Chungman KIM ,  Kwangmin PARK ,  Zhe WU ,  Seunggeun YU ,  Wonjun LEE ,  Jabin LEE ,  Jinwoo LEE

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.

    METHOD OF FABRICATING SEMICONDUCTOR DEVICES USING A TWO-STEP GAP-FILL PROCESS
    3.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICES USING A TWO-STEP GAP-FILL PROCESS 有权

    公开(公告)号：US20210050522A1

    公开(公告)日：2021-02-18

    申请号：US16746258

    申请日：2020-01-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeho JUNG ,  Youngmin KO ,  Jonguk KIM ,  Kwangmin PARK ,  Dongsung CHOI

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A method of fabricating a memory device includes forming word lines and cell stacks with gaps between the cell stacks, forming a lower gap-fill insulator in the gaps, forming an upper gap-fill insulator on the lower gap-fill insulator, curing the lower gap-fill insulator and the upper gap-fill insulator to form a gap-fill insulator, and forming bit lines on the cell stacks and the gap-fill insulator. The lower gap-fill process may be performed using a first source gas that includes first and second precursors, and the upper gap-fill process may be performed using a second source gas that includes the first and second precursors, a volume ratio of the first precursor to the second precursor in the first source gas may be greater than 15:1, and a volume ratio of the first precursor to the second precursor in the second source gas may be less than 15:1.

    MEMORY DEVICES
    5.
    发明公开
    MEMORY DEVICES 审中-公开

    公开(公告)号：US20240188305A1

    公开(公告)日：2024-06-06

    申请号：US18526031

    申请日：2023-12-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinwoo LEE ,  Hyunchul SOHN ,  Jeongwoo LEE ,  Jaeyeon KIM ,  Kwangmin PARK ,  Dongho AHN ,  Jinmyung CHOI

    IPC: H10B63/00 ,  H10B63/10

    CPC classification number: H10B63/22 ,  H10B63/10 ,  H10B63/80

    Abstract: A memory device includes a substrate; a plurality of first conductive lines on the substrate and extending in a first direction; a plurality of second conductive lines on the plurality of first conductive lines and extending in a second direction crossing the first direction; and a plurality of first memory cells respectively arranged between the plurality of first conductive lines and the plurality of second conductive lines, wherein each first memory cell of the plurality of first memory cells includes a switching device and a variable resistance material pattern, and the switching device includes a material having a composition of LaxNi1-xOy, in which 0.13≤x≤0.30 and 0.9≤y≤1.5.

    MEMORY DEVICES
    8.
    发明申请
    MEMORY DEVICES 有权

    公开(公告)号：US20210313397A1

    公开(公告)日：2021-10-07

    申请号：US17019649

    申请日：2020-09-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinwoo LEE ,  Kwangmin PARK ,  Zhe WU

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A memory device including a first conductive line on a substrate and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction that is perpendicular to the first horizontal direction; and a memory cell between the first conductive line and the second conductive line, the memory cell including a variable resistance memory layer, a buffer resistance layer, and a switch material pattern, extending in a vertical direction that is perpendicular to the first horizontal direction and the second horizontal direction, and having a tapered shape with a decreasing horizontal width along the vertical direction, wherein at least a part of the variable resistance memory layer and at least a part of the buffer resistance layer of the memory cell are at a same vertical level.

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