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公开(公告)号：US20180019392A1
公开(公告)日：2018-01-18
申请号：US15451961
申请日：2017-03-07
发明人： Jinwoo LEE , Jeonghee PARK , Dongho AHN , Zhe WU , Heeju SHIN , Ja bin LEE
CPC分类号： H01L45/141 , H01L43/08 , H01L43/10 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/16
摘要： A semiconductor memory device including first lines and second lines overlapping and intersecting each other, variable resistance memory elements disposed at intersections between the first lines and the second lines, and switching elements disposed between the variable resistance memory elements and the first lines. At least one of the switching elements includes first and second chalcogenide compound layers, and conductive nano-dots disposed between the first and second chalcogenide compound layers.
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公开(公告)号：US20240324246A1
公开(公告)日：2024-09-26
申请号：US18594355
申请日：2024-03-04
发明人： Kiyeon YANG , Donggeon GU , Bonwon KOO , Jeonghee PARK , Hajun SUNG , Dongho AHN , Zhe WU , Changseung LEE , Minwoo CHOI
CPC分类号： H10B63/24 , H10B63/84 , H10N70/841 , H10N70/8825 , H10N70/8828
摘要： Provided are a self-selecting memory device having polarity dependent threshold voltage shift characteristics and/or a memory apparatus including the self-selecting memory device. The memory device includes a first electrode, a second electrode apart from and facing the first electrode, and a memory layer between the first electrode and the second electrode. The memory layer has Ovonic threshold switching characteristics and is configured to have a threshold voltage of the memory layer be changed as a density of active traps in the memory layer is changed, the threshold voltage changing according to the polarity and the intensity of a bias voltage applied to the memory layer. Furthermore, an element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer changing.
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公开(公告)号：US20200227475A1
公开(公告)日：2020-07-16
申请号：US16567094
申请日：2019-09-11
发明人： Jeonghee PARK , Dongho AHN , Changyup PARK , Zhe WU
摘要： A variable resistance memory device including insulating patterns sequentially stacked on a substrate; first conductive lines between adjacent ones of the insulating patterns and spaced apart from each other in a first direction; a second conductive line between the first conductive lines and penetrating the insulating patterns in a third direction perpendicular to a top surface of the substrate; a phase-change pattern between the second conductive line and each of the first conductive lines and between the adjacent ones of the insulating patterns to cover a top surface of a first adjacent insulating pattern and a bottom surface of a second adjacent insulating pattern; and a selection element between the phase-change pattern and the second conductive line and between the adjacent ones of the insulating patterns to cover the top surface of the first adjacent insulating pattern and the bottom surface of the second adjacent insulating pattern.
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4.发明申请PHYSICAL VAPOR DEPOSITION METHODS AND SYSTEMS TO FORM SEMICONDUCTOR FILMS USING COUNTERBALANCE MAGNETIC FIELD GENERATORS 有权物理蒸发沉积方法和系统使用平衡磁场发生器形成半导体膜公开(公告)号：US20150311065A1
公开(公告)日：2015-10-29
申请号：US14792597
申请日：2015-07-06
发明人： Jeonghee PARK , Jae Yeol PARK
CPC分类号： H01L21/02266 , C23C14/0623 , C23C14/3407 , C23C14/35 , H01J37/32669 , H01J37/3405 , H01J37/345 , H01J37/3452 , H01J37/3455 , H01J2237/332 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625
摘要： Embodiments relate generally to semiconductor device fabrication and processes, and more particularly, to systems and methods that implement magnetic field generators configured to generate rotating magnetic fields to facilitate physical vapor deposition (“PVD”). In one embodiment, a system generates a first portion of a magnetic field adjacent a first circumferential portion of a substrate, and can generate a second portion of the magnetic field adjacent to a second circumferential portion of the substrate. The second circumferential portion is disposed at an endpoint of a diameter that passes through an axis of rotation to another endpoint of the diameter at which the first circumferential portion resides. The second peak magnitude can be less than the first peak magnitude. The system rotates the first and second portions of the magnetic fields to decompose a target material to form a plasma adjacent the substrate. The system forms a film upon the substrate.
摘要翻译： 实施例通常涉及半导体器件制造和工艺，更具体地，涉及实现磁场发生器的系统和方法，其被配置为产生旋转磁场以促进物理气相沉积（“PVD”）。 在一个实施例中，系统产生与衬底的第一周向部分相邻的磁场的第一部分，并且可以产生与衬底的第二圆周部分相邻的磁场的第二部分。 第二圆周部分设置在通过旋转轴线的直径的端点处，到达第一圆周部分所在直径的另一端点。 第二峰值可以小于第一峰值。 该系统使磁场的第一和第二部分旋转以分解目标材料以在基片附近形成等离子体。 该系统在基底上形成膜。
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公开(公告)号：US20230180641A1
公开(公告)日：2023-06-08
申请号：US18071740
申请日：2022-11-30
发明人： Zhe WU , Taeguen KIM , Jeonghee PARK , Taehyeong KIM , Minji YU
CPC分类号： H01L45/06 , H01L45/1226 , H01L27/2472 , G11C13/0011 , G11C13/0026 , G11C13/0028
摘要： A variable resistance memory device includes a substrate, a first conductive line on the substrate, the first conductive line extending in a first horizontal direction, a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction, and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell having a selection element layer, an intermediate electrode layer, and a variable resistance layer, and the variable resistance layer having a shape of stairs with a concave center.
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公开(公告)号：US20220085286A1
公开(公告)日：2022-03-17
申请号：US17384933
申请日：2021-07-26
发明人： Jeonghee PARK , Dongho AHN , Wonjun PARK
摘要： A semiconductor device includes a first conductive line on a lower structure and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction; and a memory cell structure between the first conductive line and the second conductive line. The memory cell may structure include a data storage material pattern and a selector material pattern overlapping the data storage material pattern in a vertical direction. The data storage material pattern may include a phase change material layer of InαGeβSbγTeδ. In the phase change material layer of InαGeβSbγTeδ, a sum of α and β may be lower than about 30 at. %, and a sum of γ and δ may be higher than about 70 at. %.
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公开(公告)号：US20210384256A1
公开(公告)日：2021-12-09
申请号：US17406166
申请日：2021-08-19
发明人： Si-Ho SONG , Jeonghee PARK , Changhyun CHO
摘要： A three-dimensional semiconductor memory device includes first conductive lines extending horizontally in a first direction, a second conductive line extending vertically in a second direction perpendicular to the first direction, and memory cells at cross-points between the first conductive lines and the second conductive line. The first conductive lines are laterally spaced apart from each other in a third direction crossing the first direction. Each of the memory cells includes a variable resistance element and a switching element that are horizontally arranged. The variable resistance element includes a first variable resistance pattern and a second variable resistance pattern arranged in the second direction, a first electrode between the first variable resistance pattern and the first conductive line, a second electrode between the second variable resistance pattern and the second conductive line, and a third electrode between the first variable resistance pattern and the second variable resistance pattern.
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