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    Three dimensional memory device with hybrid source electrode for wafer warpage reduction
    2.
    发明授权
    Three dimensional memory device with hybrid source electrode for wafer warpage reduction 有权
    具有用于晶片翘曲减小的混合源电极的三维存储器件

    公开(公告)号：US09524981B2

    公开(公告)日：2016-12-20

    申请号：US14703367

    申请日：2015-05-04

    申请人： SANDISK TECHNOLOGIES INC.

    发明人： Jayavel Pachamuthu ,  Johann Alsmeier

    IPC分类号： H01L27/115 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/788 ,  H01L23/522 ,  H01L23/532

    CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/53271 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    摘要： The metallic material content of a contact via structure for a three-dimensional memory device can be reduced by employing a vertical stack of a doped semiconductor material portion and a metallic fill material portion. A backside contact via can be filled with an outer metallic layer, a lower conductive material portion, an inner metallic layer, and an upper conductive material portion to form a contact via structure such that one of the lower and upper conductive material portions is a doped semiconductor material portion and the other is a metallic fill material portion. The doped semiconductor material generates less stress than the metallic fill material per volume, and thus, the contact via structure can reduce stress applied to surrounding regions in the three-dimensional memory device.

    摘要翻译： 通过采用掺杂半导体材料部分和金属填充材料部分的垂直堆叠，可以减少用于三维存储器件的接触通孔结构的金属材料含量。 背面接触通孔可以填充有外金属层，下导电材料部分，内金属层和上导电材料部分，以形成接触通孔结构，使得下导电材料部分和上导电材料部分之一是掺杂的 半导体材料部分，另一个是金属填充材料部分。 掺杂的半导体材料比每体积产生比金属填充材料更少的应力，因此，接触通孔结构可以减小施加到三维存储器件中的周围区域的应力。

    Method of integrating select gate source and memory hole for three-dimensional non-volatile memory device
    3.
    发明授权
    Method of integrating select gate source and memory hole for three-dimensional non-volatile memory device 有权
    集成三维非易失性存储器件的选择源极和存储器孔的方法

    公开(公告)号：US09524976B2

    公开(公告)日：2016-12-20

    申请号：US14341079

    申请日：2014-07-25

    申请人： SanDisk Technologies, Inc.

    发明人： Jayavel Pachamuthu ,  Johann Alsmeier ,  Henry Chien

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11551 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

    摘要： A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a carbon etch stop layer having a first width over a major surface of a substrate, forming a stack of alternating material layers over the etch stop layer, etching the stack to the etch stop layer to form a memory opening having a second width at a bottom of the memory opening that is smaller than the width of the etch stop layer, removing the etch stop layer to provide a void area having a larger width than the second width of the memory opening, forming a memory film over a sidewall of the memory opening and in the void area, and forming a semiconductor channel in the memory opening such that the memory film is located between the semiconductor channel and the sidewall of the memory opening.

    摘要翻译： 制造诸如三维NAND存储器串的半导体器件的方法包括在衬底的主表面上形成具有第一宽度的碳蚀刻停止层，在蚀刻停止层上形成交替材料层的叠层， 将该堆叠蚀刻到蚀刻停止层以形成存储器开口，该存储器开口在存储器开口的底部具有小于蚀刻停止层的宽度的第二宽度，去除蚀刻停止层以提供具有较大宽度的空隙区域 与存储器开口的第二宽度相比，在存储器开口的侧壁和空隙区域中形成记忆膜，并且在存储器开口中形成半导体沟道，使得存储膜位于半导体沟道和侧壁之间 记忆开放。

    Three dimensional NAND device having reduced wafer bowing and method of making thereof
    6.
    发明授权
    Three dimensional NAND device having reduced wafer bowing and method of making thereof 有权
    三维NAND器件具有减小的晶片弯曲及其制造方法

    公开(公告)号：US09419135B2

    公开(公告)日：2016-08-16

    申请号：US14540479

    申请日：2014-11-13

    申请人： SanDisk Technologies, Inc.

    发明人： Matthias Baenninger ,  Jayavel Pachamuthu ,  Johann Alsmeier

    IPC分类号： H01L29/78 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66

    CPC分类号： H01L29/7846 ,  H01L23/562 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, and at least one trench extending substantially perpendicular to the major surface of the substrate. The trench is filled with at least a first trench material and a second trench material. The first trench material includes a material under a first magnitude of a first stress type, and the second trench material includes a material under no stress, a second stress type opposite the first stress type, or a second magnitude of the first stress type lower than the first magnitude of the first stress type to offset warpage of the substrate due to the stress imposed by at least one of the first trench material or the plurality of control gate electrodes on the substrate.

    摘要翻译： 单片三维NAND串包括基本上平行于衬底的主表面延伸的多个控制栅极电极以及基本上垂直于衬底主表面延伸的至少一个沟槽。 沟槽填充有至少第一沟槽材料和第二沟槽材料。 第一沟槽材料包括第一应力类型的第一大小的材料，第二沟槽材料包括无应力的材料，与第一应力类型相反的第二应力类型或低于第一应力类型的第一应力类型的第二应力类型 第一应力类型的第一大小，以抵消由于基板上的至少一个第一沟槽材料或多个控制栅电极施加的应力而导致的基板的翘曲。

    Contact for vertical memory with dopant diffusion stopper and associated fabrication method
    7.
    发明授权
    Contact for vertical memory with dopant diffusion stopper and associated fabrication method 有权
    接触垂直记忆与掺杂剂扩散塞和相关制造方法

    公开(公告)号：US09406690B2

    公开(公告)日：2016-08-02

    申请号：US14572146

    申请日：2014-12-16

    申请人： SanDisk Technologies Inc.

    发明人： Liang Pang ,  Jayavel Pachamuthu ,  Yingda Dong

    IPC分类号： H01L27/115 ,  H01L27/105 ,  H01L27/112 ,  H01L29/66

    CPC分类号： H01L27/11556 ,  H01L27/1052 ,  H01L27/1128 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

    摘要： A memory device and corresponding fabrication method prevent undesired diffusion of dopants from a silicon cap of a vertical NAND string to a channel film of the NAND string. Initially, a memory hole is provided in a stack of alternating control gate layers and dielectric layers. The memory hole is filled with annular films and a dielectric core filler. The dielectric core filler is etched back from a top of the memory hole to a topmost control gate layer, forming a void. A dopant stopper liner is deposited in the void before depositing n+ doped silicon which forms the silicon cap. The dopant stopper liner can be a conductive material such as metal or polysilicon doped with carbon. A conductive via is then formed above, and aligned with, the top of the silicon cap. A bit line may be formed over the conductive via.

    摘要翻译： 存储器件和相应的制造方法防止掺杂剂从垂直NAND串的硅帽不期望地扩散到NAND串的沟道膜。 最初，在交替的控制栅极层和电介质层的堆叠中提供存储器孔。 记忆孔填充有环形膜和介质芯填料。 将介质芯填料从存储孔的顶部回蚀到最顶层的控制栅层，形成空隙。 在沉积形成硅帽的n +掺杂硅之前，在空隙中沉积掺杂剂阻挡层。 掺杂剂阻挡衬垫可以是导电材料，例如掺杂有碳的金属或多晶硅。 然后在硅帽的顶部上方形成导电通孔，并与硅帽的顶部对准。 可以在导电通孔上形成位线。

    Method of forming memory cell with high-k charge trapping layer
    8.
    发明授权
    Method of forming memory cell with high-k charge trapping layer 有权
    用高k电荷捕获层形成存储单元的方法

    公开(公告)号：US09368510B1

    公开(公告)日：2016-06-14

    申请号：US14721501

    申请日：2015-05-26

    申请人： SanDisk Technologies Inc.

    发明人： Peter Rabkin ,  Jayavel Pachamuthu ,  Johann Alsmeier ,  Masaaki Higashitani

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517

    摘要： A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to Si3N4. High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.

    摘要翻译： 公开了具有高k电荷存储区域的存储单元以及制造方法的非易失性存储装置。 电荷存储区域具有三层或更多层介电材料。 至少一层是高k材料。 与Si 3 N 4相比，高k层具有更高的陷阱密度。 电荷存储区域中的高k电介质增强了与存储单元通道的电容耦合，这可以提高存储单元电流，编程速度和擦除速度。 电荷存储区具有高 - 低 - 高导带偏移，这可以改善数据保留。 电荷存储区域具有低 - 高 - 低价带偏移，这可以改善擦除。