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公开(公告)号：US09853043B2
公开(公告)日：2017-12-26
申请号：US14834830
申请日：2015-08-25
发明人： Zhenyu Lu , Daxin Mao , Tong Zhang , Johann Alsmeier , Wenguang Shi , Henry Chien
IPC分类号： H01L27/108 , H01L29/94 , H01L27/11582 , H01L23/528 , H01L23/522 , H01L21/3205 , H01L21/3213 , H01L21/768 , H01L29/792 , H01L27/11575 , H01L27/11556 , H01L29/788 , H01L27/11548
CPC分类号： H01L27/11582 , H01L21/31144 , H01L21/32055 , H01L21/32133 , H01L21/76802 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L27/11548 , H01L27/11556 , H01L27/11575 , H01L29/7889 , H01L29/7926
摘要： A method of forming a three-dimensional memory device, includes forming a lower stack structure of insulating and first sacrificial material layers over a substrate, forming first memory openings through the lower stack structure and filling the first memory openings with a sacrificial fill material, replacing the first sacrificial material layers with first electrically conductive layers, forming an upper stack structure of insulating and second sacrificial material layers over the lower stack structure after replacing the first sacrificial material layers, forming second memory openings through the upper stack structure in areas overlying the first memory openings, replacing the second sacrificial material layers with second electrically conductive layers, removing the sacrificial fill material from the first memory openings underneath the second memory openings to form inter-stack memory openings after replacing the second sacrificial material layers, and forming memory stack structures within the inter-stack memory openings.
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公开(公告)号：US09524779B2
公开(公告)日：2016-12-20
申请号：US14313508
申请日：2014-06-24
发明人： James Kai , Henry Chien , George Matamis , Thomas Jongwan Kwon , Yao-Sheng Lee
IPC分类号： G11C16/04 , H01L27/115 , H01L29/788 , H01L29/423 , H01L29/49 , H01L21/306 , H01L21/28 , H01L21/311 , H01L21/3213 , H01L21/02 , H01L21/285 , H01L29/66
CPC分类号： G11C16/0425 , H01L21/02164 , H01L21/28273 , H01L21/28562 , H01L21/30604 , H01L21/31111 , H01L21/32133 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L29/42324 , H01L29/42328 , H01L29/4916 , H01L29/4975 , H01L29/66825 , H01L29/7883
摘要： A monolithic three dimensional NAND string including a stack of alternating first material layers and second material layers different from the first material layers over a major surface of a substrate. The first material layers include a plurality of control gate electrodes and the second material layers include an insulating material and the plurality of control gate electrodes extend in a first direction. The NAND string also includes a semiconductor channel, a blocking dielectric, and a plurality of vertically spaced apart floating gates. Each of the plurality of vertically spaced apart floating gates or each of the second material layers includes a first portion having a first thickness in the second direction, and a second portion adjacent to the first portion in the first direction and having a second thickness in the second direction which is different than the first thickness.
摘要翻译： 一种单片三维NAND串，其包括交替的第一材料层和不同于衬底的主表面上的第一材料层的第二材料层的堆叠。 第一材料层包括多个控制栅电极，第二材料层包括绝缘材料，并且多个控制栅电极沿第一方向延伸。 NAND串还包括半导体通道，阻塞电介质和多个垂直间隔开的浮动栅极。 多个垂直间隔开的浮动栅极或每个第二材料层中的每一个包括在第二方向上具有第一厚度的第一部分和在第一方向上与第一部分相邻的第二部分，并且在第二部分中具有第二厚度 第二方向与第一厚度不同。
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3.发明授权Three dimensional NAND string memory devices with voids enclosed between control gate electrodes 有权具有封闭在控制栅电极之间的空隙的三维NAND串存储器件公开(公告)号：US09356031B2
公开(公告)日：2016-05-31
申请号：US14456496
申请日：2014-08-11
发明人： Yao-Sheng Lee , Jayavel Pachamuthu , Raghuveer S. Makala , George Matamis , Johann Alsmeier , Henry Chien
IPC分类号： H01L27/115 , H01L29/66 , H01L29/788 , H01L21/764 , H01L29/06 , H01L29/51 , H01L29/423 , H01L21/28 , H01L29/10 , H01L29/792
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/28282 , H01L21/764 , H01L27/11524 , H01L27/11556 , H01L27/11568 , H01L27/1157 , H01L27/11582 , H01L29/0649 , H01L29/1033 , H01L29/42324 , H01L29/4234 , H01L29/513 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/792
摘要： A method of making a monolithic three dimensional NAND string includes forming a stack of alternating first and second material layers over a substrate, etching the stack to form a front side opening, partially removing the second material layers through the front side opening to form front side recesses, forming a first blocking dielectric in the front side recesses, forming charge storage regions over the first blocking dielectric in the front side recesses, forming a tunnel dielectric layer and a semiconductor channel over the charge storage regions in the front side opening, etching the stack to form a back side opening, removing the second material layers through the back side opening to form back side recesses using the first blocking dielectric as an etch stop, forming a second blocking dielectric in the back side recesses, and forming control gates over the second blocking dielectric in the back side recesses.
摘要翻译： 制造单片三维NAND串的方法包括在衬底上形成交替的第一和第二材料层的叠层，蚀刻叠层以形成前侧开口，通过前侧开口部分去除第二材料层以形成正面 凹部，在前侧凹部中形成第一阻挡电介质，在前侧凹部中的第一阻挡电介质的上方形成电荷存储区域，在前侧开口的电荷存储区域上形成隧道介电层和半导体沟道，蚀刻 堆叠以形成背侧开口，通过背侧开口移除第二材料层，以形成使用第一阻挡电介质作为蚀刻停止件的后侧凹槽，在后侧凹部中形成第二阻挡电介质，并在 在后侧凹槽中的第二阻挡电介质。
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4.发明授权Nanodot enhanced hybrid floating gate for non-volatile memory devices 有权用于非易失性存储器件的Nanodot增强型混合浮动栅极公开(公告)号：US09331181B2
公开(公告)日：2016-05-03
申请号：US13792662
申请日：2013-03-11
发明人： Donovan Lee , James K. Kai , George Samachisa , Henry Chien , George Matamis , Vinod R. Purayath
IPC分类号： H01L29/423 , H01L29/66 , H01L21/28 , H01L29/788 , B82Y40/00
CPC分类号： H01L29/66825 , B82Y40/00 , H01L21/28273 , H01L29/42324 , H01L29/42328 , H01L29/42332 , H01L29/7881 , H01L29/7887
摘要： A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer.
摘要翻译： 存储器件和制造存储器件的方法，该存储器件包括半导体沟道，位于半导体沟道上方的隧道介电层，位于隧道介电层上方的浮动栅极，该浮栅包括导电材料的连续层， 导电材料的至少一个突出物，面向隧道介电层并电连接到连续层，位于浮动栅极上方的阻挡电介质区域和位于阻挡电介质层上方的控制栅极。
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5.发明授权Methods of selective removal of blocking dielectric in NAND memory strings 有权选择性去除NAND存储器串中的阻塞电介质的方法公开(公告)号：US09230974B1
公开(公告)日：2016-01-05
申请号：US14468743
申请日：2014-08-26
IPC分类号： H01L29/76 , H01L27/115
CPC分类号： H01L27/11582 , H01L27/1157
摘要： Methods of making a monolithic three dimensional NAND string may enable selective removal of a blocking dielectric material, such as aluminum oxide, without otherwise damaging the device. Blocking dielectric may be selectively removed from the back side (e.g., slit trench) and/or front side (e.g., memory opening) of the NAND string. Also disclosed are NAND strings made in accordance with the embodiment methods.
摘要翻译： 制造单片三维NAND串的方法可以使得能够选择性地去除阻挡电介质材料，例如氧化铝，而不会以其他方式损坏器件。 可以从NAND串的背面（例如，狭缝沟槽）和/或前侧（例如，存储器开口）选择性地去除阻塞电介质。 还公开了根据实施方式制造的NAND串。
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6.发明授权Three dimensional NAND device with silicide containing floating gates and method of making thereof 有权具有含有浮动栅极的硅化物的三维NAND器件及其制造方法公开(公告)号：US09165940B2
公开(公告)日：2015-10-20
申请号：US14539811
申请日：2014-11-12
发明人： Henry Chien , Johann Alsmeier , George Samachisa , Henry Chin , George Matamis , Yuan Zhang , James Kai , Vinod Purayath , Donovan Lee
IPC分类号： H01L21/336 , H01L27/115 , H01L29/66 , H01L29/788 , H01L29/792 , H01L21/28 , H01L21/3205 , H01L29/49
CPC分类号： H01L27/11556 , H01L21/28273 , H01L21/32053 , H01L27/11551 , H01L27/11578 , H01L27/11582 , H01L29/4925 , H01L29/495 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers.
摘要翻译： 一种制造单片三维NAND串的方法，包括在衬底上提供交替的第一材料层和不同于第一材料层的第二材料层的堆叠，所述堆叠包括至少一个开口，其包含电荷存储材料，该电荷存储材料包括硅化物层 在所述至少一个开口中的所述电荷存储材料上的隧道电介质，以及在所述至少一个开口中的所述隧道电介质上的半导体沟道，选择性地移除所述第二材料层而不从所述堆叠中移除所述第一材料层并形成控制栅极 在第一材料层之间。
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7.发明申请METHOD OF MAKING A VERTICAL NAND DEVICE USING SEQUENTIAL ETCHING OF MULTILAYER STACKS 有权使用多层堆叠的顺序蚀刻制造垂直NAND器件的方法公开(公告)号：US20150118811A1
公开(公告)日：2015-04-30
申请号：US14585912
申请日：2014-12-30
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/822 , H01L21/8221 , H01L27/0688 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.
摘要翻译： 制造垂直NAND器件的方法包括在衬底上形成存储器堆叠的下部，在存储堆的下部形成存储器开口的下部，并至少部分地填充存储器开口的下部， 牺牲材料。 该方法还包括在存储器堆叠的下部并在牺牲材料的上方形成存储器堆叠的上部，在存储器堆叠的上部形成存储器开口的上部部分，以将下部的牺牲材料露出 部分存储器开口，去除牺牲材料以将存储器开口的下部与存储器开口的相应上部连接以形成连续的存储器开口，并在每个连续的存储器开口中形成半导体通道。
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8.发明申请THREE DIMENSIONAL NAND DEVICE WITH BIRDS BEAK CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF 有权具有BIRDS包含浮动门的三维NAND器件及其制造方法公开(公告)号：US20150008505A1
公开(公告)日：2015-01-08
申请号：US14183152
申请日：2014-02-18
发明人： Henry Chien , Donovan Lee , Vinod R. Purayath , Yuan Zhang , James K. Kai , George Matamis
IPC分类号： H01L27/115
CPC分类号： H01L27/11556 , H01L27/0688 , H01L27/11551 , H01L27/1157 , H01L27/11582 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.
摘要翻译： 一种制造单片三维NAND串的方法，包括在衬底上形成第一材料和第二材料的交替层的叠层。 第一材料包括电绝缘材料，第二材料包括半导体或导体材料。 该方法还包括蚀刻堆叠以在堆叠中形成前侧开口，在暴露在前侧开口中的第一材料和第二材料的交替层的堆叠层之上形成阻挡电介质层，形成半导体或金属电荷存储 在所述阻挡电介质上方形成在所述电荷存储层上方的隧道介电层，在所述隧道介电层上形成半导体沟道层，蚀刻所述堆叠以在所述堆叠中形成背侧开口，去除所述第一材料的至少一部分 层和介电层的部分。
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9.发明授权Vertical NAND and method of making thereof using sequential stack etching and landing pad 有权垂直NAND及其使用顺序堆栈蚀刻和着陆焊盘的方法公开(公告)号：US08884357B2
公开(公告)日：2014-11-11
申请号：US14219161
申请日：2014-03-19
发明人： Chi-Ming Wang , Johann Alsmeier , Henry Chien , Xiying Costa , Yung-Tin Chen , Christopher Petti
IPC分类号： H01L21/336 , H01L29/78 , H01L27/115
CPC分类号： H01L27/11563 , H01L27/115 , H01L27/11556 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A vertical NAND string device includes a semiconductor channel, where at least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of a substrate, at least one semiconductor or electrically conductive landing pad embedded in the semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, a blocking dielectric located adjacent to the charge storage region and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate.
摘要翻译： 垂直NAND串装置包括半导体通道，其中半导体通道的至少一个端部基本上垂直于基板的主表面延伸，至少一个半导体或导电的着陆焊盘嵌入在半导体通道中，位于 邻近半导体通道的电荷存储区域，邻近隧道电介质的电荷存储区域，位于电荷存储区域附近的阻挡电介质和基本上平行于衬底主表面延伸的多个控制栅电极。
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10.发明申请VERTICAL NAND AND METHOD OF MAKING THEREOF USING SEQUENTIAL STACK ETCHING AND LANDING PAD 有权垂直NAND及其使用顺序堆叠蚀刻和着陆垫片的方法公开(公告)号：US20140264525A1
公开(公告)日：2014-09-18
申请号：US14207012
申请日：2014-03-12
发明人： Akira Takahashi , Chi-Ming Wang , Johann Alsmeier , Henry Chien , Xiying Costa
IPC分类号： H01L27/115
CPC分类号： H01L27/11563 , H01L27/115 , H01L27/11556 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A vertical NAND string device includes a semiconductor channel, where at least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of a substrate, at least one semiconductor or electrically conductive landing pad embedded in the semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, a blocking dielectric located adjacent to the charge storage region and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate.
摘要翻译： 垂直NAND串装置包括半导体通道，其中半导体通道的至少一个端部基本上垂直于基板的主表面延伸，至少一个半导体或导电的着陆焊盘嵌入在半导体通道中，位于 邻近半导体通道的电荷存储区域，邻近隧道电介质的电荷存储区域，位于电荷存储区域附近的阻挡电介质和基本上平行于衬底主表面延伸的多个控制栅电极。
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