公开(公告)号：US20220367487A1

公开(公告)日：2022-11-17

申请号：US17317479

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peng ZHANG ,  Yanli ZHANG ,  Xiang YANG ,  Koichi MATSUNO ,  Masaaki HIGASHITANI ,  Johann ALSMEIER

IPC: H01L27/1159 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11597 ,  H01L29/06 ,  H01L21/764

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

公开(公告)号：US20240268115A1

公开(公告)日：2024-08-08

申请号：US18357702

申请日：2023-07-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Wei CAO ,  Xiang YANG ,  Koichi MATSUNO

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B43/35 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel including a first semiconductor material, and source structure including an interfacial source layer and a primary source layer. The interfacial source layer includes a second semiconductor material that has a different band gap from a band gap of the first semiconductor material and is in contact with an end portion of the vertical semiconductor channel. The primary source layer includes a third semiconductor material that has a different band gap from the band gap of the second semiconductor material, and the primary source layer is in contact with the interfacial source layer.

公开(公告)号：US20200005871A1

公开(公告)日：2020-01-02

申请号：US16024002

申请日：2018-06-29

Applicant: SanDisk Technologies LLC

Inventor： Xiang YANG ,  Aaron LEE ,  Gerrit Jan HEMINK ,  Ken OOWADA ,  Toru MIWA

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C16/04

Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.

公开(公告)号：US20190333588A1

公开(公告)日：2019-10-31

申请号：US15967270

申请日：2018-04-30

Applicant: SanDisk Technologies LLC

Inventor： Xiang YANG ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/26

Abstract: Systems and methods reduce device peak current during a read operation by charging control lines of a first set of memory cells faster than control lines of a second set of memory cells while minimizing the channel gradient formed adjacent to a selected word line to suppress occurrences of an injection read disturb in a sense line channel. For example, a first set of memory cells are in a first location relative to a selected memory cell selected for sensing, and a second set of memory cells are in a second location relative to the selected memory cell. The charge device is configured to charge the first set of memory cells and the second set of memory cells. In some aspects, a rate of charging the first set of memory cells is different from a rate of charging the second set of memory cells.

公开(公告)号：US20230197174A1

公开(公告)日：2023-06-22

申请号：US17556477

申请日：2021-12-20

Applicant: SanDisk Technologies LLC

Inventor： Jiacen GUO ,  Xiang YANG ,  Swaroop KAZA ,  Laidong WANG

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C16/3459 ,  G11C16/3409 ,  G11C16/102 ,  G11C16/26 ,  G11C16/32

Abstract: A memory device with adaptive sense time tables is disclosed. In order to maintain a desired (initial or preset) threshold voltage distribution, the sense time is adjusted as the program-erase cycle count increases. The program-erase cycle process tends to wear down memory cells, causing the QPW window to expand and the threshold voltage to widen. However, by adjusting (i.e., reducing) the sense time for increased program-erase cycles, the QPW window and the threshold voltage can be at least substantially maintained. Additionally, systems and methods for adjusting sense time based on die-to-die variations are also disclosed.

公开(公告)号：US20190304549A1

公开(公告)日：2019-10-03

申请号：US15937420

申请日：2018-03-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang YANG ,  Huai-yuan TSENG ,  Deepanshu DUTTA

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/1157

Abstract: An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a bias variance state associated with the plurality of control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.

公开(公告)号：US20200160914A1

公开(公告)日：2020-05-21

申请号：US16198593

申请日：2018-11-21

Applicant: SanDisk Technologies LLC

Inventor： Xiang YANG

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/28 ,  G11C11/56 ,  G11C16/24

Abstract: Systems and methods reduce latency during read-verify and programming operations by biasing a dummy line next to a neighboring bit line with an over-drive voltage during a first period and then biasing the dummy line to a same voltage as that of the neighboring bit line during a second period that contiguously follows the first period. The dummy line may be biased based on a state of the neighboring bit line. For example, a first dummy line is first charged to an over-drive voltage and then charged to the same voltage as that of a first neighboring bit line, and a second dummy line at an opposing edge is first charged to the over-drive voltage and then charged to the same voltage as that of a second neighboring bit line. This biasing scheme using the dummy lines helps reduce capacitive loading for neighboring bit lines during ready-verify and programming operations.