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    Imaging device or imaging system
    4.
    发明授权
    Imaging device or imaging system 有权

    公开(公告)号：US11849234B2

    公开(公告)日：2023-12-19

    申请号：US17630074

    申请日：2020-07-28

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Seiichi Yoneda ,  Hiromichi Godo ,  Yusuke Negoro ,  Hiroki Inoue ,  Takahiro Fukutome

    IPC: H04N25/75 ,  H04N25/46 ,  H04N25/71

    CPC classification number: H04N25/75 ,  H04N25/46 ,  H04N25/745

    Abstract: An imaging device with a novel structure is provided. The imaging device includes an imaging region provided with a plurality of pixels. The plurality of pixels included in the imaging region include a first pixel and a second pixel. The imaging device has a function of selecting a first region or a second region. The first region includes the same number of pixels as the second region. The first region includes at least the first and second pixels. The second region includes at least the second pixel. The pixels included in the first region or the second region have a function of outputting imaging signals obtained by the pixels. The imaging device generates first image data by concurrently reading the imaging signals output from the pixels included in the first region and performing arithmetic operation on the signals. The imaging device generates second image data by concurrently reading the imaging signals output from the pixels included in the second region and performing arithmetic operation on the signals. A first conceptual image can be generated with the use of the first image data and the second image data.

    Imaging device, operation method thereof, and electronic device
    5.
    发明授权
    Imaging device, operation method thereof, and electronic device 有权

    公开(公告)号：US11600645B2

    公开(公告)日：2023-03-07

    申请号：US17057526

    申请日：2019-06-11

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Seiichi Yoneda ,  Hidetomo Kobayashi ,  Takashi Nakagawa ,  Yusuke Negoro ,  Shunpei Yamazaki

    IPC: H01L27/146 ,  H04N5/369 ,  H04N5/353 ,  H04N5/378 ,  H04N5/3745

    Abstract: An imaging device that can obtain imaging data corresponding to high-resolution images in a short period of time is provided. The imaging device includes a pixel including a photoelectric conversion element and n (n is an integer more than 2 inclusive) retention circuits. The photoelectric conversion element and the n retention circuits are stacked. One electrode of the photoelectric conversion element is electrically connected to the first to n-th retention circuits. The retention circuits include OS transistors with an extremely low off-state current feature, and can retain imaging data for a long time. In the first to n-th periods, the imaging device obtains the first to n-th imaging data and retains it in the first to n-th retention circuits. Then, the first to n-th imaging data retained in the first to n-th retention circuits are read out. The read imaging data is output outside the imaging data through AD conversion.

    Semiconductor device and electronic device
    6.
    发明授权
    Semiconductor device and electronic device 有权

    公开(公告)号：US10255838B2

    公开(公告)日：2019-04-09

    申请号：US15654802

    申请日：2017-07-20

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Seiichi Yoneda ,  Yuki Okamoto ,  Yoshiyuki Kurokawa

    IPC: G09G3/20 ,  G09G3/36 ,  G09G3/34 ,  G09G3/32 ,  G09G3/3225

    Abstract: Provided is a semiconductor device in which power consumption and rewrite time needed for changing the parameter for color adjustment, dimming, or the like are reduced. One embodiment of a semiconductor device of the present invention includes an image processing portion including a plurality of functional circuits configured to correct image data, a plurality of scan chains corresponding to the plurality of functional circuits, and a controller controlling operations of the plurality of scan chains. During a state in which the controller controls the scan chains so that one or more scan chains chosen from the plurality of scan chains are driven and the scan chains except for the one or more scan chains are not driven, a parameter stored in one or more functional circuits connected to the one or more scan chains is rewritten.

    Storage circuit and semiconductor device
    8.
    发明授权
    Storage circuit and semiconductor device 有权
    存储电路和半导体器件

    公开(公告)号：US09438206B2

    公开(公告)日：2016-09-06

    申请号：US14471322

    申请日：2014-08-28

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yukio Maehashi ,  Seiichi Yoneda ,  Wataru Uesugi

    IPC: H03K3/356 ,  H03K3/012

    CPC classification number: H03K3/012 ,  H03K3/356 ,  H03K3/356104

    Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.

    Abstract translation: 存储电路包括第一和第二逻辑电路，其沟道形成区域包括氧化物半导体的第一和第二晶体管以及电容器。 第一和第二晶体管串联连接，电容器连接到第一和第二晶体管的连接节点。 第一晶体管用作控制第一逻辑电路的输出端子和电容器之间的连接的开关。 第二晶体管用作控制电容器和第二逻辑电路的输入端之间的连接的开关。 其相位相互反相的时钟信号被输入到第一和第二晶体管的栅极。 由于存储电路具有少量晶体管和由时钟信号控制的少量晶体管，所以存储电路是低功率电路。

    Semiconductor device and driving method thereof
    9.
    发明授权
    Semiconductor device and driving method thereof 有权
    半导体装置及其驱动方法

    公开(公告)号：US09129667B2

    公开(公告)日：2015-09-08

    申请号：US13900140

    申请日：2013-05-22

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yasuyuki Takahashi ,  Seiichi Yoneda

    IPC: G11C7/00 ,  G11C7/22 ,  G11C11/00

    CPC classification number: G11C7/22 ,  G11C11/005

    Abstract: A semiconductor device in which a nonvolatile memory can normally operate and power saving can be performed with a P-state function, and a driving method of the semiconductor device are provided. The semiconductor device includes: a first circuit configured to control a state including a driving voltage and a clock frequency of a processor core; a first memory circuit and a second memory circuit which store state data; a second circuit generating a power supply voltage and a third circuit generating a clock which are electrically connected to the first circuit; and the processor core electrically connected to the second circuit and the third circuit through a switch. The processor cores includes: a volatile memory; and a nonvolatile memory transmitting and receiving data to/from the first memory.

    Abstract translation: 可以通过P状态功能来执行其中非易失性存储器可以正常操作和省电的半导体器件，并且提供半导体器件的驱动方法。 半导体器件包括：第一电路，被配置为控制包括处理器核心的驱动电压和时钟频率的状态; 存储状态数据的第一存储器电路和第二存储器电路; 产生电源电压的第二电路和产生电连接到第一电路的时钟的第三电路; 并且处理器核心通过开关电连接到第二电路和第三电路。 处理器核心包括：易失性存储器; 以及向/从第一存储器发送和接收数据的非易失性存储器。

    Semiconductor device, method for inspecting the same, and method for driving the same
    10.
    发明授权
    Semiconductor device, method for inspecting the same, and method for driving the same 有权
    半导体装置及其检查方法及其驱动方法

    公开(公告)号：US09013937B2

    公开(公告)日：2015-04-21

    申请号：US14295816

    申请日：2014-06-04

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Seiichi Yoneda

    IPC: G11C7/00 ,  G11C29/04 ,  G11C7/10 ,  G11C29/00

    CPC classification number: G11C29/04 ,  G11C7/1009 ,  G11C29/702

    Abstract: A method for limiting writing of data to a specific memory cell without disconnecting a wiring of a memory cell array or placing a prober in contact with a memory cell, a row, or a column is provided. Row address data and column address data of a memory cell to which data cannot be written are stored in a register. Enable data which controls data writing is stored in the register. Next, in order to write data to a memory cell, row address data and column address data of a memory cell to which data is written, writing enable data, and the like are output from a logic circuit; thus, writing of data to a memory cell corresponding to the address data stored in the register is inhibited.

    Abstract translation: 提供了一种用于限制将数据写入特定存储器单元而不断开存储单元阵列的布线或将探测器与存储单元，行或列接触的方法。 不能写入数据的存储单元的行地址数据和列地址数据存储在寄存器中。 控制数据写入的数据存储在寄存器中。 接下来，为了将数据写入存储单元，从逻辑电路输出写入数据的存储单元的行地址数据和列地址数据，写使能数据等; 因此，禁止将数据写入与存储在寄存器中的地址数据相对应的存储单元。

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