公开(公告)号：US20230120515A1

公开(公告)日：2023-04-20

申请号：US18046557

申请日：2022-10-14

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Hikaru TANAKA ,  Takashi KASUGA ,  Tomoyuki SHIMODAIRA ,  Hitoshi KONDO

IPC: H01L23/532 ,  H01L23/482 ,  H01L23/522

Abstract: An interconnect substrate includes a pad for external connection and an insulating layer, wherein a portion of a lower surface of the pad is covered with the insulating layer, wherein an upper surface of the pad is situated at a lower position than an upper surface of the insulating layer, and wherein a groove whose bottom surface is formed by the insulating layer is formed around the pad in a plan view, and has an opening on an upper surface side of the insulating layer.

公开(公告)号：US20180014407A1

公开(公告)日：2018-01-11

申请号：US15635590

申请日：2017-06-28

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Junji SATO ,  Hitoshi KONDO ,  Katsuya FUKASE

IPC: H05K1/18 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H01L21/48 ,  H05K1/11 ,  H01L23/00

CPC classification number: H05K1/186 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3157 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/1434 ,  H01L2924/19041 ,  H01L2924/19102 ,  H01L2924/386 ,  H05K1/111 ,  H05K1/115 ,  H05K3/4007 ,  H05K3/424 ,  H05K3/4682 ,  H05K2201/10015 ,  H05K2201/10515 ,  H05K2201/10636 ,  H05K2201/10734 ,  H05K2201/10977

Abstract: A wiring board includes an electronic component; an insulating layer containing the electronic component therein, and including a via hole that is open at one surface of the insulating layer to expose an electrode of the electronic component; a first wiring layer embedded in the insulating layer, one surface of the first wiring layer being exposed at the one surface of the insulating layer; a second wiring layer including a wiring pattern formed on the one surface of the first wiring layer, and a via wiring extended from the wiring pattern to be extended in the via hole and directly connected to an electrode of the electronic component.

公开(公告)号：US20170179022A1

公开(公告)日：2017-06-22

申请号：US15367264

申请日：2016-12-02

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Shunichiro MATSUMOTO ,  Hitoshi KONDO ,  Katsuya FUKASE

IPC: H01L23/528 ,  H01L21/56 ,  H01L23/00 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/53228 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10175 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81022 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A wiring board includes a single-layer insulating layer, and a single-layer interconnect layer embedded in the insulating layer, wherein an entirety of a first surface of the interconnect layer is exposed in a recessed position relative to a first surface of the insulating layer, and a second surface of the interconnect layer is partially exposed in a recessed position relative to a second surface of the insulating layer.

公开(公告)号：US20250113438A1

公开(公告)日：2025-04-03

申请号：US18884616

申请日：2024-09-13

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Tomoyuki SHIMODAIRA ,  Kiyoshi OI ,  Hitoshi KONDO

IPC: H05K1/18 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/64 ,  H05K1/11 ,  H05K3/42

Abstract: A wiring board includes a first interconnect structure including a first interconnect layer and a first insulating layer, a second interconnect structure, including a second interconnect layer and a second insulating layer, and laminated on one side of the first interconnect structure, and a third interconnect structure, including a third interconnect layer and a third insulating layer, and laminated on the other side of the first interconnect structure. The second interconnect layer has an interconnect density higher than those of the first and the third interconnect layers. The first insulating layer has a through hole penetrating the first insulating layer, and an electronic component electrically connected to the second interconnect layer is disposed inside the through hole. An embedding resin covering the electronic component is provided inside the through hole, and extends to cover the first insulating layer and fills in between the first and second insulating layers.

公开(公告)号：US20230123522A1

公开(公告)日：2023-04-20

申请号：US17937831

申请日：2022-10-04

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Hikaru TANAKA ,  Takashi KASUGA ,  Tomoyuki SHIMODAIRA ,  Hitoshi KONDO

IPC: H05K1/11

Abstract: A wiring board includes a pad configured to make an external electrical connection, and an insulating layer. A portion of a lower surface of the pad is covered with the insulating layer. The pad includes a base portion, and an extending portion formed integrally with the base portion and extending toward an outer periphery of a side surface of the base portion in a plan view at a lower end of the side surface of the base portion. The insulating layer is provided with a groove that is located in a periphery of the pad in the plan view, exposes a side surface of the pad, and opens to an upper surface of the insulating layer.

公开(公告)号：US20190371717A1

公开(公告)日：2019-12-05

申请号：US16418168

申请日：2019-05-21

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yoshihiro KITA ,  Hitoshi KONDO

IPC: H01L23/498 ,  H05K1/02 ,  H05K1/09 ,  H01L21/48

Abstract: An interconnect substrate includes an insulating layer having a first resin layer and a second resin layer covering an upper surface of the first resin layer, a first conductive layer having an upper surface and side surfaces covered with the first resin layer, a lower surface of the first conductive layer being exposed from a lower surface of the first resin layer, and a second conductive layer including an interconnect pattern and a via interconnect, the interconnect pattern being disposed on an upper surface of the second resin layer, the via interconnect penetrating through both the second resin layer and the first resin layer to connect the interconnect pattern to the upper surface of the first conductive layer, wherein the first resin layer is made of a resin having a higher modulus of elasticity and a lower coefficient of elongation than the second resin layer.