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    SEMICONDUCTOR PACKAGE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE 有权
    半导体封装

    公开(公告)号：US20140124921A1

    公开(公告)日：2014-05-08

    申请号：US13799362

    申请日：2013-03-13

    申请人： SK HYNIX INC.

    发明人： Sang Eun LEE ,  Sung Soo RYU ,  Chang Il KIM ,  Seon Kwang JEON

    IPC分类号： H01L23/498

    CPC分类号： H01L25/0652 ,  H01L23/16 ,  H01L23/3128 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/06155 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/15311

    摘要： A semiconductor package includes a substrate; a driving chip having first bumps on a first surface and bump pads on a second surface facing away from the first surface, and mounted to the substrate by the medium of the first bumps; a support member disposed on the substrate substantially horizontally with respect to the driving chip; and a plurality of memory chips substantially horizontally disposed on the driving chip and the support member such that one corner portions of the memory chips are positioned on the driving chip while being centered about the driving chip, wherein the respective memory chips have second bumps which are electrically connected with the respective bump pads of the driving chip, on one surfaces of the one corner portions of the memory chips which face the driving chip.

    摘要翻译： 半导体封装包括基板; 驱动芯片，其在第一表面上具有第一凸块，并且在第二表面上具有凸起焊盘，所述第二表面背离所述第一表面，并且通过所述第一凸块的介质安装到所述基板; 相对于所述驱动芯片基本上水平地布置在所述基板上的支撑构件; 以及基本上水平地设置在驱动芯片和支撑构件上的多个存储器芯片，使得存储芯片的一个角部位于驱动芯片上，同时围绕驱动芯片居中，其中各个存储器芯片具有第二凸块， 在与驱动芯片相对的存储芯片的一个角部的一个表面上与驱动芯片的各个凸块焊盘电连接。

    SEMICONDUCTOR PACKAGE
    2.
    发明申请
    SEMICONDUCTOR PACKAGE 有权
    半导体封装

    公开(公告)号：US20140117430A1

    公开(公告)日：2014-05-01

    申请号：US13798800

    申请日：2013-03-13

    申请人： SK HYNIX INC.

    发明人： Sang Eun LEE ,  Sung Soo RYU ,  Chang Il KIM ,  Seon Kwang JEON

    IPC分类号： H01L25/18

    CPC分类号： H01L25/18 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5385 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/9202 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

    摘要： A semiconductor package includes a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate.

    摘要翻译： 半导体封装包括第一衬底，水平地设置在第一衬底上的多个存储器芯片，并且具有面对第一衬底的一个表面，远离一个表面的其他表面以及形成在其它表面上的第一凸块， 第二基板，设置在所述多个存储器芯片上并电连接;副基板，与所述多个存储器芯片一起水平地设置在所述第一基板上，并且电连接所述第一基板和所述第二基板;以及驱动芯片， 并且安装到第二基板，使得第二凸块与第二基板电连接。

    SEMICONDUCTOR CHIP INCLUDING A SPARE BUMP AND STACKED PACKAGE HAVING THE SAME
    3.
    发明申请
    SEMICONDUCTOR CHIP INCLUDING A SPARE BUMP AND STACKED PACKAGE HAVING THE SAME 有权
    半导体芯片，包括一个备用BUMP和堆叠的包装

    公开(公告)号：US20150084689A1

    公开(公告)日：2015-03-26

    申请号：US14179842

    申请日：2014-02-13

    申请人： SK hynix Inc.

    发明人： Sang Eun LEE ,  Chang Il KIM

    IPC分类号： H01L23/538 ,  H01L25/065

    CPC分类号： H01L25/0657 ,  G11C29/025 ,  G11C29/702 ,  G11C29/848 ,  G11C2029/4402 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/13025 ,  H01L2224/14515 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/37001

    摘要： A stacked package including: a semiconductor substrate, a circuit layer formed over the semiconductor substrate, a bump formed over the circuit layer, a spare bump formed correspondingly to the bump and over the circuit layer, and configured for replacing the bump with the spare bump, a through electrode configuring to pass through the semiconductor substrate on a same line as the bump and electrically coupled the bump or the spare bump in response to a selection signal, and a spare through electrode configured to pass through the semiconductor substrate on a same line as the spare bump and electrically coupled with the bump or the spare bump in response to a selection signal. When a bump has failed, a vertical input/output line of the semiconductor chips is established by a spare bump corresponding to the failed bump through the selective signal routing.

    摘要翻译： 一种堆叠封装，包括：半导体衬底，形成在所述半导体衬底上的电路层，形成在所述电路层上的凸块，与所述凸块相对应地形成在所述电路层上的备用凸起，并且被配置为用所述备用凸块 ，通孔，其构造成在与所述凸块相同的线上穿过所述半导体衬底，并且响应于选择信号电连接所述凸起或所述备用凸起;以及备用通电极，被配置为在相同的线上穿过所述半导体衬底 作为备用凸块并响应于选择信号与凸块或备用凸起电耦合。 当碰撞失败时，半导体芯片的垂直输入/输出线通过通过选择信号路由对应于失效凸块的备用凸块来建立。

    CHIP DIE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    4.
    发明申请
    CHIP DIE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
    芯片和半导体存储器件包括它们

    公开(公告)号：US20140241079A1

    公开(公告)日：2014-08-28

    申请号：US13948616

    申请日：2013-07-23

    申请人： SK hynix Inc.

    发明人： Seon Kwang JEON ,  Sung Soo RYU ,  Chang Il KIM

    IPC分类号： G11C7/00

    CPC分类号： G11C5/04 ,  G11C7/1048 ,  G11C7/1069

    摘要： A chip die including a first input/output (I/O) pad configured to transmit/receive an I/O signal of a memory cell array included in the chip die; a second I/O pad configured to, if a stacked chip die exists on the chip die, transmit/receive a via I/O signal of the stacked chip die, and configured to, if the stacked chip die does not exist on the chip die, transmit/receive a differential I/O signal of the chip die; and an I/O driver configured to receive an operation mode signal including information as to whether the stacked chip die exists on the chip die in such a manner that the second I/O pad is configured to transmit/receive the via I/O signal or the differential I/O signal.

    摘要翻译： 一种芯片裸片，其包括被配置为发送/接收芯片芯片中包括的存储单元阵列的I / O信号的第一输入/输出（I / O） 第二I / O焊盘，其被配置为：如果芯片芯片上存在堆叠芯片裸片，则发送/接收堆叠芯片管芯的通孔I / O信号，并且如果堆叠芯片裸片不存在于芯片上 模块，发送/接收芯片芯片的差分I / O信号; 以及I / O驱动器，其被配置为接收包括关于所述堆叠芯片管芯是否存在于所述芯片管芯上的信息的操作模式信号，使得所述第二I / O焊盘被配置为发送/接收所述通孔I / O信号 或差分I / O信号。

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20140328104A1

    公开(公告)日：2014-11-06

    申请号：US14071230

    申请日：2013-11-04

    申请人： SK hynix Inc.

    发明人： Seon Kwang JEON ,  Sung Soo RYU ,  Chang Il KIM ,  Jang Ryul KIM

    IPC分类号： G11C5/02

    CPC分类号： G11C5/025 ,  G11C5/04 ,  H01L25/0657 ,  H01L2224/16145

    摘要： A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and second internal input/output circuit units for exchanging signals; first external input/output circuit unit for exchanging signals through first external input/output pads formed according to an external interface standard of a first memory over the second surface; and second external input/output circuit unit for exchanging signals through second external input/output pads formed according to an external interface standard of a second memory over the second surface, wherein semiconductor device operates in one of a first mode in which the first internal input/output circuit unit and the first external input/output circuit unit are enabled and a second mode in which the first and second internal input/output circuit units and the second external input/output circuit unit are enabled.

    摘要翻译： 堆叠在逻辑芯片上的逻辑芯片和存储器芯片，逻辑芯片具有面向存储器芯片的第一表面和与第一表面相对的第二表面，并且包括：用于交换信号的第一和第二内部输入/输出电路单元; 第一外部输入/输出电路单元，用于通过在第二表面上的第一存储器的外部接口标准形成的第一外部输入/输出焊盘交换信号; 以及第二外部输入/输出电路单元，用于通过在第二表面上根据第二存储器的外部接口标准形成的第二外部输入/输出焊盘来交换信号，其中半导体器件以第一模式中的一个工作，其中第一内部输入 /输出电路单元和第一外部输入/输出电路单元被使能，其中第一和第二内部输入/输出电路单元和第二外部输入/输出电路单元被使能的第二模式。

    STACK PACKAGE
    6.
    发明申请
    STACK PACKAGE 有权
    堆叠包

    公开(公告)号：US20140285253A1

    公开(公告)日：2014-09-25

    申请号：US13941929

    申请日：2013-07-15

    申请人： SK hynix Inc.

    发明人： Seon Kwang JEON ,  Chang Il KIM

    IPC分类号： G11C8/12 ,  H01L25/065

    CPC分类号： G11C8/12 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A stack package may include a plurality of chips stacked with a plurality of layers; and a chip selection controller configured to provide a reference and chip selection control signal to the plurality of chips. Each chip may comprise: a reference signal controller configured to transmit the reference signal through a first line interconnecting the plurality of chips; a chip selection delay unit configured to control a delay timing point of the chip selection control signal to transmit the control result to each node of a second line interconnecting the plurality of chips; a delay-time-difference sensing unit configured to calculate a delay time difference between a signal applied to each node of the first and second line to generate chip selection information corresponding to the calculated delay time difference; and a memory unit configured to store the chip selection information.

    摘要翻译： 堆叠封装可以包括堆叠有多个层的多个芯片; 以及芯片选择控制器，被配置为向所述多个芯片提供参考和芯片选择控制信号。 每个芯片可以包括：参考信号控制器，被配置为通过互连所述多个芯片的第一线路来发送参考信号; 芯片选择延迟单元，被配置为控制芯片选择控制信号的延迟定时点，以将控制结果发送到互连所述多个芯片的第二线路的每个节点; 延迟时间差感测单元，被配置为计算施加到所述第一和第二行的每个节点的信号之间的延迟时间差，以产生与所计算的延迟时间差相对应的码片选择信息; 以及存储单元，被配置为存储芯片选择信息。