公开(公告)号：US20140124921A1

公开(公告)日：2014-05-08

申请号：US13799362

申请日：2013-03-13

Applicant: SK HYNIX INC.

Inventor： Sang Eun LEE ,  Sung Soo RYU ,  Chang Il KIM ,  Seon Kwang JEON

IPC: H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/16 ,  H01L23/3128 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/06155 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/15311

Abstract: A semiconductor package includes a substrate; a driving chip having first bumps on a first surface and bump pads on a second surface facing away from the first surface, and mounted to the substrate by the medium of the first bumps; a support member disposed on the substrate substantially horizontally with respect to the driving chip; and a plurality of memory chips substantially horizontally disposed on the driving chip and the support member such that one corner portions of the memory chips are positioned on the driving chip while being centered about the driving chip, wherein the respective memory chips have second bumps which are electrically connected with the respective bump pads of the driving chip, on one surfaces of the one corner portions of the memory chips which face the driving chip.

Abstract translation: 半导体封装包括基板; 驱动芯片，其在第一表面上具有第一凸块，并且在第二表面上具有凸起焊盘，所述第二表面背离所述第一表面，并且通过所述第一凸块的介质安装到所述基板; 相对于所述驱动芯片基本上水平地布置在所述基板上的支撑构件; 以及基本上水平地设置在驱动芯片和支撑构件上的多个存储器芯片，使得存储芯片的一个角部位于驱动芯片上，同时围绕驱动芯片居中，其中各个存储器芯片具有第二凸块， 在与驱动芯片相对的存储芯片的一个角部的一个表面上与驱动芯片的各个凸块焊盘电连接。

公开(公告)号：US20150106678A1

公开(公告)日：2015-04-16

申请号：US14167880

申请日：2014-01-29

Applicant: SK HYNIX INC.

Inventor： Seon Kwang JEON

IPC: G06F11/10

CPC classification number: G06F11/1048 ,  G06F11/1008 ,  G06F11/1032 ,  G11C7/1006 ,  G11C11/4096 ,  G11C2029/0411

Abstract: A semiconductor system includes a memory configured to output a parity bit during a read operation and receive a data mask (DM) signal during a write operation. The semiconductor system also includes a System On Chip (SOC) configured to detect errors by decoding the parity bit during the read operation, and output the DM signal to the memory during the write operation. Since the parity bit is generated in the memory based on data received from outside the memory, the semiconductor device and a corresponding semiconductor system may reduce the size of a storage space for parity bits.

Abstract translation: 半导体系统包括被配置为在读取操作期间输出奇偶校验位并在写操作期间接收数据掩码（DM）信号的存储器。 半导体系统还包括片上系统（SOC），其配置为通过在读取操作期间对奇偶校验位进行解码来检测错误，并且在写入操作期间将DM信号输出到存储器。 由于基于从存储器外部接收的数据在存储器中产生奇偶校验位，所以半导体器件和对应的半导体系统可以减小用于奇偶校验位的存储空间的大小。

公开(公告)号：US20150029805A1

公开(公告)日：2015-01-29

申请号：US14176026

申请日：2014-02-07

Applicant: SK HYNIX INC.

Inventor： Seon Kwang JEON ,  Sung Soo RYU ,  Chang il KIM

IPC: G11C5/02 ,  G11C5/14

CPC classification number: G11C5/14 ,  G11C5/025

Abstract: A semiconductor memory device includes a plurality of first regions formed in a line-type and extending in a first direction, and a plurality of second regions and a plurality of third regions arranged between adjacent first regions in a zigzag manner.

Abstract translation: 一种半导体存储器件包括以线型形成并沿第一方向延伸的多个第一区域和多个第二区域和多个第三区域，其以锯齿形的方式布置在相邻的第一区域之间。

公开(公告)号：US20140117430A1

公开(公告)日：2014-05-01

申请号：US13798800

申请日：2013-03-13

Applicant: SK HYNIX INC.

Inventor： Sang Eun LEE ,  Sung Soo RYU ,  Chang Il KIM ,  Seon Kwang JEON

IPC: H01L25/18

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5385 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/9202 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate.

Abstract translation: 半导体封装包括第一衬底，水平地设置在第一衬底上的多个存储器芯片，并且具有面对第一衬底的一个表面，远离一个表面的其他表面以及形成在其它表面上的第一凸块， 第二基板，设置在所述多个存储器芯片上并电连接;副基板，与所述多个存储器芯片一起水平地设置在所述第一基板上，并且电连接所述第一基板和所述第二基板;以及驱动芯片， 并且安装到第二基板，使得第二凸块与第二基板电连接。

公开(公告)号：US20140014958A1

公开(公告)日：2014-01-16

申请号：US13737394

申请日：2013-01-09

Applicant: SK HYNIX INC.

Inventor： Tac Keun OH ,  Jae Sung OH ,  Kwon Whan HAN ,  Woong Sun LEE ,  Seon Kwang JEON

IPC: H01L21/66

CPC classification number: H01L22/00 ,  H01L22/32 ,  H01L23/481 ,  H01L23/5256 ,  H01L23/5258 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06565

Abstract: A semiconductor chip module includes a first semiconductor chip having first through-electrodes, a second semiconductor chip having second through-electrodes which are electrically connected with the first through-electrodes, first and second test pads, a first connection line which connects the first test pad with one second through-electrode, a second connection line which connects the second test pad with another second through-electrode, third connection lines which connect the remaining second through-electrodes into pairs, and are partially constituted by fuses, and a third semiconductor chip having fourth connection lines which electrically connect the first through-electrodes of the first semiconductor chip into pairs, wherein the first and second is through-electrodes are connected in series between the first test pad and the second test pad by the first connection line, the second connection line, the third connection lines, and the fourth connection lines.

Abstract translation: 半导体芯片模块包括具有第一通孔的第一半导体芯片，具有与第一通孔电连接的第二贯通电极的第二半导体芯片，第一和第二测试焊盘，连接第一测试 具有一个第二贯通电极的焊盘，连接第二测试焊盘与另一个第二贯通电极的第二连接线，将剩余的第二贯通电极成对连接并部分地由保险丝构成的第三连接线，以及第三半导体 芯片具有将第一半导体芯片的第一贯通电极电连接成对的第四连接线，其中，第一和第二直通电极通过第一连接线串联连接在第一测试焊盘和第二测试焊盘之间， 第二连接线，第三连接线和第四连接线。

公开(公告)号：US20170329547A1

公开(公告)日：2017-11-16

申请号：US15334421

申请日：2016-10-26

Applicant: SK hynix Inc.

Inventor： Seon Kwang JEON ,  Bo Ra CHOI

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F1/32 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0653 ,  G06F3/0658 ,  G06F3/0673 ,  G06F12/0607 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14

Abstract: A bank interleaving controller may include a power calculator and a write driver. The power calculator may calculate a total power consumption by adding a power consumption of one or more memory banks that are performing write operations and an amount of power that is expected to be additionally consumed to write input data. The write driver may write the input data to a memory cell corresponding to an input address when the total power consumption is equal to or less than a reference power consumption.

公开(公告)号：US20150048957A1

公开(公告)日：2015-02-19

申请号：US14154588

申请日：2014-01-14

Applicant: SK HYNIX INC.

Inventor： Seon Kwang JEON

IPC: H03M9/00

CPC classification number: H03M9/00

Abstract: A data input/output (I/O) device includes a plurality of data units and an I/O assembly. The plurality of data units is coupled to a global I/O (GIO) line through corresponding local I/O (LIO) lines and configured to receive or transmit a plurality of data groups through the corresponding LIO lines. At least one of the plurality of data units have a different operation speed. The I/O assembly performs serial/parallel conversion operations on the plurality of data groups including a high-speed data group and outputs results of the serial/parallel conversion operations. The high-speed data group is output from the at least one of the plurality of data units having the different operation speed.

Abstract translation: 数据输入/输出（I / O）设备包括多个数据单元和I / O组件。 多个数据单元通过相应的本地I / O（LIO）线耦合到全局I / O（GIO）线并且被配置为通过相应的LIO线接收或发送多个数据组。 多个数据单元中的至少一个具有不同的操作速度。 I / O组件对包括高速数据组的多个数据组执行串行/并行转换操作，并输出串行/并行转换操作的结果。 高速数据组从具有不同操作速度的多个数据单元中的至少一个输出。

公开(公告)号：US20140241079A1

公开(公告)日：2014-08-28

申请号：US13948616

申请日：2013-07-23

Applicant: SK hynix Inc.

Inventor： Seon Kwang JEON ,  Sung Soo RYU ,  Chang Il KIM

IPC: G11C7/00

CPC classification number: G11C5/04 ,  G11C7/1048 ,  G11C7/1069

Abstract: A chip die including a first input/output (I/O) pad configured to transmit/receive an I/O signal of a memory cell array included in the chip die; a second I/O pad configured to, if a stacked chip die exists on the chip die, transmit/receive a via I/O signal of the stacked chip die, and configured to, if the stacked chip die does not exist on the chip die, transmit/receive a differential I/O signal of the chip die; and an I/O driver configured to receive an operation mode signal including information as to whether the stacked chip die exists on the chip die in such a manner that the second I/O pad is configured to transmit/receive the via I/O signal or the differential I/O signal.

Abstract translation: 一种芯片裸片，其包括被配置为发送/接收芯片芯片中包括的存储单元阵列的I / O信号的第一输入/输出（I / O） 第二I / O焊盘，其被配置为：如果芯片芯片上存在堆叠芯片裸片，则发送/接收堆叠芯片管芯的通孔I / O信号，并且如果堆叠芯片裸片不存在于芯片上 模块，发送/接收芯片芯片的差分I / O信号; 以及I / O驱动器，其被配置为接收包括关于所述堆叠芯片管芯是否存在于所述芯片管芯上的信息的操作模式信号，使得所述第二I / O焊盘被配置为发送/接收所述通孔I / O信号 或差分I / O信号。

公开(公告)号：US20150102837A1

公开(公告)日：2015-04-16

申请号：US14135302

申请日：2013-12-19

Applicant: SK HYNIX INC.

Inventor： Seon Kwang JEON

IPC: H03K19/003 ,  H03K19/20

CPC classification number: H03K19/003 ,  H03K19/20

Abstract: A semiconductor device is implemented with a technology for removing a command bubbling generated when performing a rank-to-rank switching on chips that are stacked and interconnected through a through silicon via (TSV). The semiconductor device includes a first memory, a second memory stacked over the first memory to input/output data through a TSV, and an arbiter configured to adjust first data received from the first memory and second data received from the second memory through the TSV and provide the adjusted data to an input/output (I/O) pad.

Abstract translation: 半导体器件通过一种技术来实现，该技术用于去除在通过硅通孔（TSV）堆叠和互连的芯片上执行秩到等级切换时产生的命令冒泡。 半导体器件包括第一存储器，堆叠在第一存储器上以通过TSV输入/输出数据的第二存储器和被配置为调整从第一存储器接收的第一数据和通过TSV从第二存储器接收的第二数据的仲裁器，以及 将调整后的数据提供给输入/输出（I / O）板。

公开(公告)号：US20140328104A1

公开(公告)日：2014-11-06

申请号：US14071230

申请日：2013-11-04

Applicant: SK hynix Inc.

Inventor： Seon Kwang JEON ,  Sung Soo RYU ,  Chang Il KIM ,  Jang Ryul KIM

IPC: G11C5/02

CPC classification number: G11C5/025 ,  G11C5/04 ,  H01L25/0657 ,  H01L2224/16145

Abstract: A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and second internal input/output circuit units for exchanging signals; first external input/output circuit unit for exchanging signals through first external input/output pads formed according to an external interface standard of a first memory over the second surface; and second external input/output circuit unit for exchanging signals through second external input/output pads formed according to an external interface standard of a second memory over the second surface, wherein semiconductor device operates in one of a first mode in which the first internal input/output circuit unit and the first external input/output circuit unit are enabled and a second mode in which the first and second internal input/output circuit units and the second external input/output circuit unit are enabled.

Abstract translation: 堆叠在逻辑芯片上的逻辑芯片和存储器芯片，逻辑芯片具有面向存储器芯片的第一表面和与第一表面相对的第二表面，并且包括：用于交换信号的第一和第二内部输入/输出电路单元; 第一外部输入/输出电路单元，用于通过在第二表面上的第一存储器的外部接口标准形成的第一外部输入/输出焊盘交换信号; 以及第二外部输入/输出电路单元，用于通过在第二表面上根据第二存储器的外部接口标准形成的第二外部输入/输出焊盘来交换信号，其中半导体器件以第一模式中的一个工作，其中第一内部输入 /输出电路单元和第一外部输入/输出电路单元被使能，其中第一和第二内部输入/输出电路单元和第二外部输入/输出电路单元被使能的第二模式。