公开(公告)号：US08975528B2

公开(公告)日：2015-03-10

申请号：US13590470

申请日：2012-08-21

Applicant: Shuuichi Kariyazaki

Inventor： Shuuichi Kariyazaki

IPC: H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H05K1/11 ,  H05K7/00 ,  B23K31/02 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02

CPC classification number: H05K1/111 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/17051 ,  H01L2224/17104 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/82385 ,  H01L2924/15311 ,  H05K1/0268 ,  H05K2201/09663 ,  H05K2201/10734 ,  H05K2201/10977 ,  Y02P70/611 ,  H01L2924/00

Abstract: Even in an electronic device where electrodes are coupled electrically using a solder, sections to which electrodes of an electronic component are coupled are switched by a method other than changing circuits of the electronic component or changing circuits of a wiring substrate.The electronic device includes: a wiring substrate having two or more first electrodes over one surface thereof; and an electronic component having, over one surface thereof, two or more second electrodes arranged corresponding to the two or more first electrodes, respectively. At least one of the first electrodes is a specific electrode divided into two or more divided portions, and the divided portions are coupled to different wirings, respectively. Further, at least one of the divided portions is coupled to a corresponding second electrode through a solder.

Abstract translation: 即使在使用焊料电极电连接的电子装置中，电子部件的电极所连接的部分也可以通过除了电子部件的电路或配线基板的改变电路之外的方法进行切换。 电子设备包括：在其一个表面上具有两个或更多个第一电极的布线基板; 以及电子部件，在其一个表面上分别具有对应于两个或更多个第一电极排列的两个或更多个第二电极。 第一电极中的至少一个是分为两个或更多个分割部分的特定电极，并且分割部分分别耦合到不同的布线。 此外，分割部分中的至少一个通过焊料耦合到对应的第二电极。

公开(公告)号：US08947886B2

公开(公告)日：2015-02-03

申请号：US13186112

申请日：2011-07-19

Applicant: Joachim Mahler ,  Manfred Mengel ,  Khalil Hosseini ,  Klaus Schmidt ,  Franz-Peter Kalz

Inventor： Joachim Mahler ,  Manfred Mengel ,  Khalil Hosseini ,  Klaus Schmidt ,  Franz-Peter Kalz

IPC: H05K7/00 ,  H05K1/16 ,  H01L23/00

CPC classification number: H01L24/83 ,  H01L24/00 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/245 ,  H01L2224/2499 ,  H01L2224/26165 ,  H01L2224/27462 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/82002 ,  H01L2224/82101 ,  H01L2224/82345 ,  H01L2224/82385 ,  H01L2224/82986 ,  H01L2224/831 ,  H01L2224/83851 ,  H01L2224/92144 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.

Abstract translation: 电子部件包括导电载体。 导电载体包括载体表面，半导体芯片包括芯片表面。 载体表面和芯片表面中的一个或两个包括非平面结构。 芯片附着到载体上，其芯片表面面向载体表面，使得由于载体表面和第一芯片表面中的一个或两个的非平面结构，在芯片表面和载体表面之间提供间隙 。 电子部件还包括位于间隙中的第一电沉积金属层。

公开(公告)号：US09275877B2

公开(公告)日：2016-03-01

申请号：US13236952

申请日：2011-09-20

Applicant: Yaojian Lin ,  Rui Huang ,  Heap Hoe Kuan ,  Seng Guan Chow

Inventor： Yaojian Lin ,  Rui Huang ,  Heap Hoe Kuan ,  Seng Guan Chow

IPC: H01L21/60 ,  H01L21/56 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/82385 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/92247 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/0665 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first insulating layer formed over a carrier. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer. Vias are formed through the second insulating layer. A second conductive layer is formed over the second insulating layer and extends into the vias. A semiconductor die is mounted to the second conductive layer. A bond wire is formed between a contact pad on the semiconductor die and the second conductive layer. The second conductive layer extends to a mounting site of the semiconductor die to minimize the bond wire span. An encapsulant is deposited over the semiconductor die. A portion of the first insulating layer is removed to expose the second conductive layer. A portion of the first conductive layer is removed to electrically isolate remaining portions of the first conductive layer.

Abstract translation: 半导体器件具有形成在载体上的第一绝缘层。 在第一绝缘层上形成第一导电层。 在第一导电层上形成第二绝缘层。 通过第二绝缘层形成通孔。 第二导电层形成在第二绝缘层上并延伸到通孔中。 半导体管芯安装到第二导电层。 在半导体管芯上的接触焊盘和第二导电层之间形成接合线。 第二导电层延伸到半导体管芯的安装位置，以使接合线跨距最小化。 密封剂沉积在半导体管芯上。 去除第一绝缘层的一部分以露出第二导电层。 去除第一导电层的一部分以电隔离第一导电层的剩余部分。

公开(公告)号：US08929092B2

公开(公告)日：2015-01-06

申请号：US13504281

申请日：2010-10-28

Applicant: Shingo Yoshioka ,  Hiroaki Fujiwara ,  Hiromitsu Takashita ,  Tsuyoshi Takeda

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara ,  Hiromitsu Takashita ,  Tsuyoshi Takeda

IPC: H05K7/00 ,  H05K3/10 ,  H05K1/11 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H05K3/38 ,  H05K3/18

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/82385 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K3/107 ,  H05K3/184 ,  H05K3/38 ,  H05K2201/0373 ,  H05K2201/0391 ,  H05K2201/09736 ,  H05K2201/2072 ,  H05K2203/0307 ,  H05K2203/0565 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A circuit board includes an electric circuit having a wiring section and a pad section in the surface of an insulating base substrate. The electric circuit is configured such that a conductor is embedded in a circuit recess formed in the surface of the insulating base substrate, and the surface roughness of the conductor is different in the wiring section and the pad section of the electric circuit. In this case, it is preferable that the surface roughness of the conductor in the pad section is greater than the surface roughness of the conductor in the wiring section.

Abstract translation: 电路板包括在绝缘基底的表面上具有布线部分和焊盘部分的电路。 电路被配置为使得导体嵌入形成在基底绝缘体的表面中的电路凹槽中，并且导体的表面粗糙度在电路的布线部分和焊盘部分中是不同的。 在这种情况下，优选的是，焊盘部中的导体的表面粗糙度大于布线部中的导体的表面粗糙度。

公开(公告)号：US20130077275A1

公开(公告)日：2013-03-28

申请号：US13590470

申请日：2012-08-21

Applicant: Shuuichi KARIYAZAKI

Inventor： Shuuichi KARIYAZAKI

IPC: H05K1/16 ,  H05K1/02 ,  B23K31/02 ,  H05K7/06

CPC classification number: H05K1/111 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/17051 ,  H01L2224/17104 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/82385 ,  H01L2924/15311 ,  H05K1/0268 ,  H05K2201/09663 ,  H05K2201/10734 ,  H05K2201/10977 ,  Y02P70/611 ,  H01L2924/00

Abstract: Even in an electronic device where electrodes are coupled electrically using a solder, sections to which electrodes of an electronic component are coupled are switched by a method other than changing circuits of the electronic component or changing circuits of a wiring substrate.The electronic device includes: a wiring substrate having two or more first electrodes over one surface thereof; and an electronic component having, over one surface thereof, two or more second electrodes arranged corresponding to the two or more first electrodes, respectively. At least one of the first electrodes is a specific electrode divided into two or more divided portions, and the divided portions are coupled to different wirings, respectively. Further, at least one of the divided portions is coupled to a corresponding second electrode through a solder.

Abstract translation: 即使在使用焊料电极电连接的电子装置中，电子部件的电极所连接的部分也可以通过除了电子部件的电路或配线基板的改变电路之外的方法进行切换。 电子设备包括：在其一个表面上具有两个或更多个第一电极的布线基板; 以及电子部件，在其一个表面上分别具有对应于两个或更多个第一电极排列的两个或更多个第二电极。 第一电极中的至少一个是分为两个或更多个分割部分的特定电极，并且分割部分分别耦合到不同的布线。 此外，分割部分中的至少一个通过焊料耦合到对应的第二电极。

公开(公告)号：US20130021766A1

公开(公告)日：2013-01-24

申请号：US13186112

申请日：2011-07-19

Applicant: Joachim Mahler ,  Manfred Mengel ,  Khalil Hosseini ,  Klaus Schmidt ,  Franz-Peter Kalz

Inventor： Joachim Mahler ,  Manfred Mengel ,  Khalil Hosseini ,  Klaus Schmidt ,  Franz-Peter Kalz

IPC: H05K1/11 ,  H05K3/30 ,  H05K1/18

CPC classification number: H01L24/83 ,  H01L24/00 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/245 ,  H01L2224/2499 ,  H01L2224/26165 ,  H01L2224/27462 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/82002 ,  H01L2224/82101 ,  H01L2224/82345 ,  H01L2224/82385 ,  H01L2224/82986 ,  H01L2224/831 ,  H01L2224/83851 ,  H01L2224/92144 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.

公开(公告)号：US09646853B1

公开(公告)日：2017-05-09

申请号：US14883638

申请日：2015-10-15

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Kai Yun Yow ,  Poh Leng Eu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/2405 ,  H01L2224/241 ,  H01L2224/24227 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73217 ,  H01L2224/73265 ,  H01L2224/82104 ,  H01L2224/82385 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92144 ,  H01L2924/1433 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01046

Abstract: A patterned, non-conductive substrate for an integrated circuit (IC) package has a die side configured to receive a die and a lead side opposite the die side. A pattern formed in the substrate defines openings (e.g., holes, steps, grooves, and/or cavities) that extend between the die side and the lead side of the substrate. In the IC package, the openings are filled with conductive material (e.g., solder) that supports electrical connections between bond pads on the die and leads formed from the conductive material. The substrate can be used to form a relatively inexpensive, quad flat no-lead (QFN) IC package without using a metal lead frame and without bond wires.

公开(公告)号：US20150111343A1

公开(公告)日：2015-04-23

申请号：US14581653

申请日：2014-12-23

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Manfred Mengel ,  Khalil Hosseini ,  Klaus Schmidt ,  Franz-Peter Kalz

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/00 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/245 ,  H01L2224/2499 ,  H01L2224/26165 ,  H01L2224/27462 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/82002 ,  H01L2224/82101 ,  H01L2224/82345 ,  H01L2224/82385 ,  H01L2224/82986 ,  H01L2224/831 ,  H01L2224/83851 ,  H01L2224/92144 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.

Abstract translation: 电子部件包括导电载体。 导电载体包括载体表面，半导体芯片包括芯片表面。 载体表面和芯片表面中的一个或两个包括非平面结构。 芯片附着到载体上，其芯片表面面向载体表面，使得由于载体表面和第一芯片表面之一或两者的非平面结构，在芯片表面和载体表面之间提供间隙 。 电子部件还包括位于间隙中的第一电沉积金属层。

公开(公告)号：US20140183751A1

公开(公告)日：2014-07-03

申请号：US14196363

申请日：2014-03-04

Applicant: PANASONIC CORPORATION

Inventor： Shingo YOSHIOKA ,  Hiroaki FUJIWARA ,  Hiromitsu TAKASHITA ,  Tsuyoshi TAKEDA

IPC: H01L23/482

CPC classification number: G11B5/486 ,  H01L21/4846 ,  H01L21/565 ,  H01L22/12 ,  H01L23/145 ,  H01L23/3121 ,  H01L23/49866 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82385 ,  H01L2224/82399 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15798 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/386 ,  H01L2924/3862 ,  H05K1/111 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  H05K2203/1461 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, the three-dimensional structure having an insulating resin layer that contains a filler formed from at least one element selected from typical non-metal elements and typical metal elements, wherein a recessed gutter for wiring is formed on a surface of the insulating resin layer, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

Abstract translation: 本发明的一个方面是一种三维结构，其中在表面上形成布线，所述三维结构具有绝缘树脂层，所述绝缘树脂层含有由选自典型非金属元素中的至少一种元素形成的填料和 典型的金属元件，其中在绝缘树脂层的表面上形成用于布线的凹槽，并且布线导体的至少一部分嵌入到凹槽中用于布线。

公开(公告)号：US20120206891A1

公开(公告)日：2012-08-16

申请号：US13504281

申请日：2010-10-28

Applicant: Shingo Yoshioka ,  Hiroaki Fujiwara ,  Hiromitsu Takashita ,  Tsuyoshi Takeda

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara ,  Hiromitsu Takashita ,  Tsuyoshi Takeda

IPC: H05K7/06 ,  H05K1/02

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/82385 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K3/107 ,  H05K3/184 ,  H05K3/38 ,  H05K2201/0373 ,  H05K2201/0391 ,  H05K2201/09736 ,  H05K2201/2072 ,  H05K2203/0307 ,  H05K2203/0565 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A circuit board H10 according to the present invention is a circuit board H10 in which an electric circuit H6 including a wiring section H6a and a pad section H6b is provided in the surface of an insulating base substrate H1. The electric circuit H6 is configured such that a conductor H5 is embedded in a circuit recess H3 formed in the surface of the insulating base substrate H1, and the surface roughness of the conductor H5 is different in the wiring section H6a and the pad section H6b of the electric circuit H6. In this case, it is preferable that the surface roughness of the conductor H5 in the pad section H6b is greater than the surface roughness of the conductor H5 in the wiring section H6a.

Abstract translation: 根据本发明的电路板H10是电路板H10，其中包括布线部分H6a和焊盘部分H6b的电路H6设置在绝缘基板H1的表面中。 电路H6被配置为使得导体H5嵌入在形成在绝缘性基板H1的表面上的电路凹部H3中，并且导体H5的表面粗糙度在布线部H6a和焊盘部H6b中不同 电路H6。 在这种情况下，优选的是，焊盘部H6b中的导体H5的表面粗糙度大于布线部H6a中的导体H5的表面粗糙度。