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公开(公告)号:US20140268591A1
公开(公告)日:2014-09-18
申请号:US14204800
申请日:2014-03-11
CPC分类号: H01L24/95 , H01L21/563 , H01L23/3121 , H01L24/06 , H01L24/24 , H01L24/25 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L25/0655 , H01L25/072 , H01L25/0753 , H01L25/18 , H01L25/50 , H01L33/20 , H01L2221/68381 , H01L2224/06181 , H01L2224/24137 , H01L2224/25105 , H01L2224/25174 , H01L2224/32225 , H01L2224/73267 , H01L2224/82101 , H01L2224/82104 , H01L2224/82143 , H01L2224/92244 , H01L2224/95085 , H01L2224/95101 , H01L2224/95102 , H01L2224/95115 , H01L2224/95143 , H01L2224/95146 , H01L2924/10253 , H01L2924/12 , H01L2924/1203 , H01L2924/12041 , H01L2924/13 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H05K1/029 , H05K1/0296 , H05K3/12
摘要: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.
摘要翻译: 可编程电路包括微阵列晶体管或二极管的印刷组阵列。 这些装置被预先形成并印刷成油墨并固化。 每个组中的设备并联连接,以使每个组充当单个设备。 在一个实施例中,每个组中包含约10个设备,因此冗余使得每个组非常可靠。 每个组具有终止于衬底上的贴片区域中的至少一个电引线。 互连导体图案将贴片区域中的组的至少一些引线互连以产生用于通用电路的定制应用的逻辑电路。 这些组也可以互连成逻辑门,并且栅极引线终止于贴片区域。 然后,互连导体图案将形成复合逻辑电路的栅极互连。
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公开(公告)号:US20170135214A1
公开(公告)日:2017-05-11
申请号:US15405601
申请日:2017-01-13
CPC分类号: H05K1/0296 , H01L21/563 , H01L23/3121 , H01L24/06 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L24/95 , H01L25/0655 , H01L25/072 , H01L25/0753 , H01L25/18 , H01L25/50 , H01L33/20 , H01L2221/68381 , H01L2224/06181 , H01L2224/24137 , H01L2224/25105 , H01L2224/25174 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/82101 , H01L2224/82104 , H01L2224/82143 , H01L2224/92244 , H01L2224/95085 , H01L2224/95101 , H01L2224/95102 , H01L2224/95115 , H01L2224/95143 , H01L2224/95146 , H01L2924/10253 , H01L2924/12 , H01L2924/1203 , H01L2924/12041 , H01L2924/13 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091
摘要: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.
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公开(公告)号:US08722513B2
公开(公告)日:2014-05-13
申请号:US13391063
申请日:2011-02-22
申请人: Jae-Hak Lee , Chang-Woo Lee , Joon-Yub Song , Tae-Ho Ha
发明人: Jae-Hak Lee , Chang-Woo Lee , Joon-Yub Song , Tae-Ho Ha
CPC分类号: H01L23/488 , H01L21/50 , H01L24/26 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/04042 , H01L2224/26145 , H01L2224/27013 , H01L2224/29139 , H01L2224/2919 , H01L2224/29191 , H01L2224/32145 , H01L2224/48091 , H01L2224/73215 , H01L2224/73265 , H01L2224/82143 , H01L2224/83002 , H01L2224/83051 , H01L2224/83143 , H01L2224/83192 , H01L2224/9205 , H01L2224/92147 , H01L2225/0651 , H01L2225/06562 , H01L2225/06593 , H01L2924/00014 , H01L2924/10253 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: The present invention relates to a semiconductor chip stack package and a manufacturing method thereof, and more particularly, to a semiconductor chip stack package and a manufacturing method thereof in which a plurality of chips can be rapidly arranged and bonded without a precise device or operation so as to improve productivity.
摘要翻译: 半导体芯片堆叠封装及其制造方法技术领域本发明涉及一种半导体芯片堆叠封装及其制造方法,更具体地,涉及一种半导体芯片堆叠封装及其制造方法,其中可以在没有精确的装置或操作的情况下快速地布置和粘合多个芯片 以提高生产率。
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4.
公开(公告)号:US08513061B2
公开(公告)日:2013-08-20
申请号:US13031861
申请日:2011-02-22
申请人: Jae-Hak Lee , Chang-Woo Lee , Joon-Yub Song , Tae-Ho Ha
发明人: Jae-Hak Lee , Chang-Woo Lee , Joon-Yub Song , Tae-Ho Ha
CPC分类号: H01L21/76898 , H01L24/03 , H01L24/05 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05669 , H01L2224/13009 , H01L2224/24011 , H01L2224/24146 , H01L2224/24226 , H01L2224/245 , H01L2224/27416 , H01L2224/27452 , H01L2224/2761 , H01L2224/27616 , H01L2224/29187 , H01L2224/821 , H01L2224/82101 , H01L2224/82143 , H01L2224/83001 , H01L2224/83013 , H01L2224/83143 , H01L2224/83192 , H01L2224/92 , H01L2224/9202 , H01L2224/92244 , H01L2225/06513 , H01L2225/06541 , H01L2924/01029 , H01L2924/00014 , H01L2224/03 , H01L2224/27 , H01L2224/83 , H01L2924/01074 , H01L2924/01013
摘要: The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.
摘要翻译: 本发明涉及一种用于3D封装的硅通孔(TSV),用于集成半导体器件及其制造方法,更具体地,涉及一种用于半导体器件的3D封装的贯穿硅通孔(TSV),其具有能够 提高生产效率,具有非常高的导电性和最小化电信号延迟,而不用通过在低温状态下自对准衬底并顺序地接合多个半导体管芯(或半导体芯片)而使用载体晶片,以及 制造相同。
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5.
公开(公告)号:US20180132347A1
公开(公告)日:2018-05-10
申请号:US15868773
申请日:2018-01-11
CPC分类号: H05K1/0296 , H01L21/563 , H01L23/3121 , H01L24/00 , H01L24/06 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L24/95 , H01L25/0655 , H01L25/072 , H01L25/0753 , H01L25/18 , H01L25/50 , H01L33/20 , H01L2221/68381 , H01L2224/06181 , H01L2224/24137 , H01L2224/25105 , H01L2224/25174 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/82101 , H01L2224/82104 , H01L2224/82143 , H01L2224/92244 , H01L2224/95085 , H01L2224/95101 , H01L2224/95102 , H01L2224/95115 , H01L2224/95143 , H01L2224/95146 , H01L2924/10253 , H01L2924/12 , H01L2924/1203 , H01L2924/12041 , H01L2924/13 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091
摘要: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.
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公开(公告)号:US20170125372A1
公开(公告)日:2017-05-04
申请号:US15408930
申请日:2017-01-18
CPC分类号: H01L24/95 , H01L21/563 , H01L23/3121 , H01L24/06 , H01L24/24 , H01L24/25 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L25/0655 , H01L25/072 , H01L25/0753 , H01L25/18 , H01L25/50 , H01L33/20 , H01L2221/68381 , H01L2224/06181 , H01L2224/24137 , H01L2224/25105 , H01L2224/25174 , H01L2224/32225 , H01L2224/73267 , H01L2224/82101 , H01L2224/82104 , H01L2224/82143 , H01L2224/92244 , H01L2224/95085 , H01L2224/95101 , H01L2224/95102 , H01L2224/95115 , H01L2224/95143 , H01L2224/95146 , H01L2924/10253 , H01L2924/12 , H01L2924/1203 , H01L2924/12041 , H01L2924/13 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H05K1/029 , H05K1/0296 , H05K3/12
摘要: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.
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7.
公开(公告)号:US09412728B2
公开(公告)日:2016-08-09
申请号:US14418842
申请日:2013-07-19
发明人: Carlotta Guiducci , Yusuf Leblebici , Yuksel Temiz
CPC分类号: H01L25/50 , G03F7/2022 , G03F7/32 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3185 , H01L24/02 , H01L24/05 , H01L24/24 , H01L24/27 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2221/68381 , H01L2224/02313 , H01L2224/0239 , H01L2224/05166 , H01L2224/05624 , H01L2224/24011 , H01L2224/24051 , H01L2224/24146 , H01L2224/27002 , H01L2224/32145 , H01L2224/73267 , H01L2224/82002 , H01L2224/82005 , H01L2224/8201 , H01L2224/82101 , H01L2224/82106 , H01L2224/82143 , H01L2224/83143 , H01L2224/83203 , H01L2224/8385 , H01L2224/9202 , H01L2224/9205 , H01L2224/92244 , H01L2224/94 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/01322 , H01L2924/10253 , H01L2924/1461 , H01L2924/00014 , H01L2924/01013 , H01L2924/00013 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要: A method for performing a post processing pattern on a diced chip having a footprint, comprises the steps of providing a support wafer; applying a first dry film photoresist to the support wafer; positioning a mask corresponding to the footprint of the diced chip on the first dry film photoresist; expose the mask and the first dry film photoresist to UV radiation; remove the mask; photoresist develop the exposed first dry film photoresist to obtain a cavity corresponding to the diced chip; positioning the diced chip inside the cavity; applying a second dry film photoresist to the first film photoresist and the diced chip; and expose and develop the second dry film photoresist applied to the diced chip in accordance with the post processing pattern.
摘要翻译: 一种用于在具有覆盖区的切割芯片上执行后处理图案的方法,包括以下步骤:提供支撑晶片; 将第一干膜光致抗蚀剂施加到所述支撑晶片; 将对应于切割的芯片的覆盖区的掩模定位在第一干膜光致抗蚀剂上; 将掩模和第一干膜光致抗蚀剂暴露于UV辐射; 取下面具; 光致抗蚀剂显影曝光的第一干膜光致抗蚀剂以获得与切割芯片相对应的空腔; 将切割的芯片定位在腔内; 将第二干膜光致抗蚀剂施加到第一膜光致抗蚀剂和切割的芯片上; 并且根据后处理图案曝光和显影施加到切割的芯片上的第二干膜光致抗蚀剂。
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公开(公告)号:US20160111408A1
公开(公告)日:2016-04-21
申请号:US14967629
申请日:2015-12-14
IPC分类号: H01L25/00 , H01L25/075
CPC分类号: H01L25/50 , H01L21/6836 , H01L24/05 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/75 , H01L24/76 , H01L24/82 , H01L24/83 , H01L24/95 , H01L24/96 , H01L25/0753 , H01L2221/68327 , H01L2221/68381 , H01L2221/68386 , H01L2224/04026 , H01L2224/05655 , H01L2224/13101 , H01L2224/24225 , H01L2224/245 , H01L2224/291 , H01L2224/32225 , H01L2224/75252 , H01L2224/75283 , H01L2224/75655 , H01L2224/75701 , H01L2224/75733 , H01L2224/75801 , H01L2224/76655 , H01L2224/76701 , H01L2224/76733 , H01L2224/76801 , H01L2224/82002 , H01L2224/82102 , H01L2224/82143 , H01L2224/83002 , H01L2224/83143 , H01L2224/83191 , H01L2224/8323 , H01L2224/83801 , H01L2224/9202 , H01L2224/95101 , H01L2224/95144 , H01L2924/00011 , H01L2924/10253 , H01L2924/10272 , H01L2924/1033 , H01L2924/12041 , H01L2924/12042 , H01L2924/12044 , H01L2924/3511 , H01L2933/0066 , H01L2924/014 , H01L2924/01047 , H01L2924/00 , H01L2224/83205 , H01L2924/00014
摘要: Disclosed herein is a method of assembling an array of light emitting diode (LED) dies on a substrate comprising: positioning dies in fluid; exposing the dies to a magnetic force to attract the dies onto magnets that are arranged at pre-determined locations either on or near the substrate; and forming permanent connections between the dies and the substrate thereby constituting an array of LED dies on a substrate.
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公开(公告)号:US20140284795A1
公开(公告)日:2014-09-25
申请号:US14011930
申请日:2013-08-28
申请人: SK hynix Inc.
发明人: Sang Eun LEE , Chang Il KIM
IPC分类号: H01L23/00
CPC分类号: H01L24/06 , H01L23/13 , H01L23/49883 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/83 , H01L24/92 , H01L2224/06155 , H01L2224/24105 , H01L2224/24226 , H01L2224/24227 , H01L2224/244 , H01L2224/245 , H01L2224/24997 , H01L2224/25175 , H01L2224/2612 , H01L2224/27436 , H01L2224/27442 , H01L2224/29015 , H01L2224/29036 , H01L2224/2919 , H01L2224/32225 , H01L2224/8201 , H01L2224/82097 , H01L2224/82105 , H01L2224/82138 , H01L2224/82143 , H01L2224/82385 , H01L2224/82815 , H01L2224/8291 , H01L2224/83138 , H01L2224/83192 , H01L2224/83855 , H01L2224/92144 , H01L2224/92244 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
摘要: Various embodiments are directed to a semiconductor package and a method for manufacturing the same. A semiconductor package includes the following: a substrate having a plurality of connection pads; a semiconductor chip provided with a plurality of bonding pads on a first surface thereof and attached onto the substrate in a face-down position so that the bonding pads are positioned right above the corresponding connection pads; and thermoplastic conductive members introduced between the substrate and the semiconductor chip such that the bonding pad and the corresponding connection pad may be electrically connected.
摘要翻译: 各种实施例涉及半导体封装及其制造方法。 半导体封装包括以下:具有多个连接焊盘的衬底; 半导体芯片,其在其第一表面上设置有多个接合焊盘,并以面朝下的位置附接到所述基板上,使得所述接合焊盘位于相应的连接焊盘的正上方; 以及引入在基板和半导体芯片之间的热塑性导电构件,使得焊盘和相应的连接焊盘可以电连接。
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公开(公告)号:US09245875B2
公开(公告)日:2016-01-26
申请号:US14394501
申请日:2013-04-19
IPC分类号: H01L25/075 , H01L23/00 , H01L21/683
CPC分类号: H01L25/50 , H01L21/6836 , H01L24/05 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/75 , H01L24/76 , H01L24/82 , H01L24/83 , H01L24/95 , H01L24/96 , H01L25/0753 , H01L2221/68327 , H01L2221/68381 , H01L2221/68386 , H01L2224/04026 , H01L2224/05655 , H01L2224/13101 , H01L2224/24225 , H01L2224/245 , H01L2224/291 , H01L2224/32225 , H01L2224/75252 , H01L2224/75283 , H01L2224/75655 , H01L2224/75701 , H01L2224/75733 , H01L2224/75801 , H01L2224/76655 , H01L2224/76701 , H01L2224/76733 , H01L2224/76801 , H01L2224/82002 , H01L2224/82102 , H01L2224/82143 , H01L2224/83002 , H01L2224/83143 , H01L2224/83191 , H01L2224/8323 , H01L2224/83801 , H01L2224/9202 , H01L2224/95101 , H01L2224/95144 , H01L2924/00011 , H01L2924/10253 , H01L2924/10272 , H01L2924/1033 , H01L2924/12041 , H01L2924/12042 , H01L2924/12044 , H01L2924/3511 , H01L2933/0066 , H01L2924/014 , H01L2924/01047 , H01L2924/00 , H01L2224/83205 , H01L2924/00014
摘要: Disclosed herein is a method of assembling an array of light emitting diode (LED) dies on a substrate comprising: positioning dies in fluid; exposing the dies to a magnetic force to attract the dies onto magnets that are arranged at pre-determined locations either on or near the substrate; and forming permanent connections between the dies and the substrate thereby constituting an array of LED dies on a substrate.
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