-
公开(公告)号:US20170264304A1
公开(公告)日:2017-09-14
申请号:US15455901
申请日:2017-03-10
Applicant: SOCIONEXT INC.
Inventor: Ian Juso DEDIC , Gavin Lambertus Allen , Bernd Hans Germann , Albert Hubert Dorner
IPC: H03L7/085
CPC classification number: H03L7/085 , G04F10/005 , H03L7/091
Abstract: There is disclosed herein current-mode circuitry for measuring a timing difference between first and second signals, the circuitry comprising: a tail node configured during a measurement operation to receive a current pulse in dependence upon the first signal; first and second nodes conductively connectable to said tail node along respective first and second paths; and steering circuitry configured during the measurement operation to control such connections between the tail node and the first and second nodes based on the second signal to steer the current pulse so that a first portion of the current pulse passes along the first path and a second portion of the current pulse passes along the second path in dependence upon the timing difference between said first and second signals; and a signal output unit configured to output a measurement-result signal indicating a measure of said timing difference based upon one or both of the first and second portions.
-
公开(公告)号:US09444479B2
公开(公告)日:2016-09-13
申请号:US14553598
申请日:2014-11-25
Applicant: SOCIONEXT INC.
Inventor: Ian Juso Dedic , Gavin Lambertus Allen
IPC: H03M1/12 , H03M1/06 , G11C27/02 , H01H9/54 , H03K17/00 , H03M1/10 , H03L7/00 , H03M1/08 , H03L7/091 , H03M1/00
CPC classification number: H03M1/0614 , G11C27/02 , H01H9/54 , H03K17/00 , H03L7/00 , H03L7/091 , H03M1/002 , H03M1/0881 , H03M1/1009 , H03M1/12 , H03M1/121 , H03M1/1215 , H03M1/1245 , H03M1/126 , Y10T307/76
Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.
Abstract translation: 公开了被配置为由基本正弦时钟信号驱动的电流模式时间交织采样电路。 这种电路可以并入ADC电路中,例如作为IC芯片上的集成电路。 所公开的电路能够自行校准而不脱机。
-
公开(公告)号:US10075172B2
公开(公告)日:2018-09-11
申请号:US15455901
申请日:2017-03-10
Applicant: SOCIONEXT INC.
Inventor: Ian Juso Dedic , Gavin Lambertus Allen , Bernd Hans Germann , Albert Hubert Dorner
Abstract: There is disclosed herein current-mode circuitry for measuring a timing difference between first and second signals, the circuitry comprising: a tail node configured during a measurement operation to receive a current pulse in dependence upon the first signal; first and second nodes conductively connectable to said tail node along respective first and second paths; and steering circuitry configured during the measurement operation to control such connections between the tail node and the first and second nodes based on the second signal to steer the current pulse so that a first portion of the current pulse passes along the first path and a second portion of the current pulse passes along the second path in dependence upon the timing difference between said first and second signals; and a signal output unit configured to output a measurement-result signal indicating a measure of said timing difference based upon one or both of the first and second portions.
-
公开(公告)号:US09201813B2
公开(公告)日:2015-12-01
申请号:US14025313
申请日:2013-09-12
Applicant: SOCIONEXT INC.
Inventor: Ian Juso Dedic , Gavin Lambertus Allen
IPC: H03K17/687 , G06F13/00 , G06F1/10
CPC classification number: G06F13/00 , G06F1/10 , G06F13/4072
Abstract: Signal distribution circuitry for use in an integrated circuit, the signal distribution circuitry comprising: first and second output nodes, for connection to respective output signal lines; first and second supply nodes for connection to respective high and low voltage sources; and switching circuitry connected to the first and second output nodes and the first and second supply nodes and operable based on an input signal to conductively connect the first and second output nodes either to the first and second supply nodes, respectively, in a first state when the input signal has a first value, or to each other, in a second state when the input signal has a second value different from the first value, so as to transmit output signals dependent on the input signal via such output signal lines.
Abstract translation: 用于集成电路的信号分配电路,所述信号分配电路包括:第一和第二输出节点,用于连接到相应的输出信号线; 用于连接到相应的高压和低压源的第一和第二供电节点; 以及连接到第一和第二输出节点以及第一和第二供应节点的开关电路,并且可以基于输入信号进行操作,以在第一状态下分别将第一和第二输出节点导电地连接到第一和第二供应节点, 当输入信号具有与第一值不同的第二值时,输入信号具有第一值,或者彼此相关,以便经由这样的输出信号线发送取决于输入信号的输出信号。
-
公开(公告)号:US09973186B2
公开(公告)日:2018-05-15
申请号:US14473706
申请日:2014-08-29
Applicant: SOCIONEXT INC.
Inventor: Ian Juso Dedic , Saul Darzy , Gavin Lambertus Allen
CPC classification number: H03K17/145 , H03K17/162 , H03K17/302 , H03M1/0617 , H03M1/662 , H03M1/687 , H03M1/745 , H03M1/747
Abstract: Switching circuitry for use in a digital-to-analog converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node.
-
公开(公告)号:US09344060B2
公开(公告)日:2016-05-17
申请号:US14473630
申请日:2014-08-29
Applicant: SOCIONEXT INC.
Inventor: Ian Juso Dedic , Gavin Lambertus Allen
CPC classification number: H03H17/08 , G06F1/04 , G06F1/12 , H03B27/00 , H03H2218/04 , H03H2218/12 , H03K5/135 , H03K5/1502 , H03M1/0624
Abstract: Signal-alignment circuitry, comprising: phase-rotation circuitry connected to receive one or more input clock signals and operable to generate therefrom one or more output clock signals; and control circuitry operable to control the amount of phase rotation applied by the phase-rotation circuitry to carry out a plurality of alignment operations, the alignment operations comprising: one or more first operations each comprising rotating one or more of said output clock signals relative to one or more of the other said output clock signals, to bring a phase relationship between said output clock signals, or clock signals derived therefrom, towards or into a given phase relationship; and one or more second operations each comprising rotating all of said output clock signals together, to bring a phase relationship between said output or derived clock signals and said input clock signals or an external-reference signal towards or into a given phase relationship.
Abstract translation: 信号对准电路,包括:相位旋转电路,被连接以接收一个或多个输入时钟信号并且可操作以从其产生一个或多个输出时钟信号; 以及控制电路,其可操作以控制由所述相位旋转电路施加的相位旋转量以执行多个对准操作,所述对准操作包括:一个或多个第一操作,每个包括使所述输出时钟信号中的一个或多个相对于 一个或多个其它所述输出时钟信号,以使所述输出时钟信号之间的相位关系或从其导出的时钟信号朝给定的相位关系; 以及一个或多个第二操作,每个包括将所有所述输出时钟信号全部旋转在一起,以使得所述输出或导出的时钟信号与所述输入时钟信号之间的相位关系或向给定相位关系的外部参考信号。
-
-
-
-
-