公开(公告)号：US20230136705A1

公开(公告)日：2023-05-04

申请号：US17976798

申请日：2022-10-29

Applicant: SPTS Technologies Limited

Inventor： Scott Haymore ,  Adrian Thomas ,  Tony Wilby ,  Stephen Burgess

IPC: H01L33/00 ,  H01L33/50

Abstract: A substrate is positioned on a substrate supporting upper surface of a substrate support. An arrangement of permanent magnets is positioned beneath the substrate supporting upper surface so that permanent magnets are disposed underneath the substrate. The deposition material is deposited into the recesses formed in the substrate by sputtering a sputtering material from a target of a magnetron device. While depositing the deposition material, the arrangement of permanent magnets provides a substantially uniform lateral magnetic field across the surface of the substrate which extends into a region beyond a periphery of the substrate to enhance resputtering of deposited material deposited into the recesses.

公开(公告)号：US11913109B2

公开(公告)日：2024-02-27

申请号：US16541635

申请日：2019-08-15

Applicant: SPTS Technologies Limited

Inventor： Tony Wilby ,  Steve Burgess ,  Adrian Thomas ,  Rhonda Hyndman ,  Scott Haymore ,  Clive Widdicks ,  Ian Moncrieff

IPC: C23C14/50 ,  C23C14/34 ,  C23C14/35 ,  C23C14/54 ,  H01J37/32 ,  H01J37/34

CPC classification number: C23C14/50 ,  C23C14/345 ,  C23C14/3485 ,  C23C14/35 ,  C23C14/351 ,  C23C14/505 ,  H01J37/32715 ,  H01J37/3405 ,  H01J37/3452 ,  H01J37/3455 ,  H01J37/3467 ,  C23C14/542

Abstract: A magnet assembly is disclosed for steering ions used in the formation of a material layer upon a substrate during a pulsed DC physical vapour deposition process. Apparatus and methods are also disclosed incorporating the assembly for controlling thickness variation in a material layer formed via pulsed DC physical vapour deposition. The magnet assembly comprises a magnetic field generating arrangement for generating a magnetic field proximate the substrate and means for rotating the ion steering magnetic field generating arrangement about an axis of rotation, relative to the substrate. The magnetic field generating arrangement comprises a plurality of magnets configured to an array which extends around the axis of rotation, wherein the array of magnets are configured to generate a varying magnetic field strength along a radial direction relative to the axis of rotation.

公开(公告)号：US20240177997A1

公开(公告)日：2024-05-30

申请号：US18244904

申请日：2023-09-11

Applicant: SPTS Technologies Limited

Inventor： Scott Haymore ,  Tony Wilby ,  Steve Burgess

IPC: H01L21/285 ,  C23C14/02 ,  C23C14/34 ,  H01J37/32 ,  H01J37/34 ,  H01L21/02

CPC classification number: H01L21/2855 ,  C23C14/021 ,  C23C14/345 ,  H01J37/32082 ,  H01J37/3464 ,  H01L21/02068 ,  H01J2237/332 ,  H01J2237/335

Abstract: A PVD apparatus can perform a cleaning step and a deposition step on an electrically conductive feature formed on a semiconductor substrate. The semiconductor substrate with the electrically conductive feature thereon can be positioned on the substrate support. A cleaning step can be performed to remove material from the electrically conductive feature predominantly by etching with ions of an inert gas while the target is simultaneously sputtered. A deposition step is performed by applying no RF bias to the substrate support or applying an RF bias which is less than the RF bias applied to the substrate support during the cleaning step and supplying an electrical signal having an associated electrical power to the target. The RF bias, if present, and electrical power are sufficient to deposit an electrically conductive deposition material onto the electrically conductive feature by PVD.

公开(公告)号：US20220085275A1

公开(公告)日：2022-03-17

申请号：US17461928

申请日：2021-08-30

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Scott Haymore ,  Adrian Thomas ,  Tony Wilby

IPC: H01L41/316 ,  H01L41/08 ,  H01L41/187 ,  H01L41/319 ,  C23C14/06 ,  C23C14/00 ,  C01B21/06

Abstract: Pulsed DC reactive sputtering of a target deposits an additive-containing aluminium nitride film onto a metallic layer of a semiconductor substrate. The additive-containing aluminium nitride film contains an additive element selected from scandium, yttrium, titanium, chromium, magnesium and hafnium. Depositing the additive-containing aluminium nitride film includes introducing a gaseous mixture comprising nitrogen gas and an inert gas into the chamber at a flow rate, in which the flow rate of the gaseous mixture comprises a nitrogen gas flow rate, and in which the nitrogen gas flow rate is less than or equal to about 50% of the flow rate of the gaseous mixture and also is sufficient to fully poison the target.

公开(公告)号：US12207556B2

公开(公告)日：2025-01-21

申请号：US16865227

申请日：2020-05-01

Applicant: SPTS Technologies Limited

Inventor： Adrian Thomas ,  Steve Burgess ,  Amit Rastogi ,  Tony Wilby ,  Scott Haymore

IPC: H03H3/08 ,  C01B21/06 ,  C23C14/00 ,  C23C14/02 ,  C23C14/06 ,  H03H3/02 ,  H03H9/02 ,  H03H9/17 ,  H10N30/045 ,  H10N30/076 ,  H10N30/082

Abstract: In a method for sputter depositing an additive-containing aluminium nitride film containing an additive element like Sc or Y, a first layer of the additive-containing aluminium nitride film is deposited onto a substrate disposed within a chamber by pulsed DC reactive sputtering. A second layer of the additive-containing aluminium nitride film is deposited onto the first layer by pulsed DC reactive sputtering. The second layer has the same composition as the first layer. A gas or gaseous mixture is introduced into the chamber when depositing the first layer. A gaseous mixture comprising nitrogen gas and an inert gas is introduced into the chamber when depositing the second layer. The percentage of nitrogen gas in the flow rate (in sccm) when depositing the first layer is greater than that when depositing the second layer.

公开(公告)号：US11361975B2

公开(公告)日：2022-06-14

申请号：US16601358

申请日：2019-10-14

Applicant: SPTS Technologies Limited

Inventor： Tony Wilby ,  Steve Burgess

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/768

Abstract: A method of fabricating an integrated circuit is disclosed. The method of removing excess metal of a metal interconnection layer during integrated circuit fabrication process comprises the steps of: plasma etching an excess metal portion of the metal interconnection layer using plasma comprising a noble gas, for an etch duration. The method further comprises stopping the etch process prior to the excess metal portion being completely removed and thus prior to a dielectric surface upon which the metal interconnection is formed, becoming completely exposed. The remaining excess metal portion comprising excess metal residues is subsequently removed using a second etch step.