公开(公告)号：US09721921B2

公开(公告)日：2017-08-01

申请号：US15012346

申请日：2016-02-01

申请人： STATS ChipPAC, Ltd.

发明人： KyungMoon Kim ,  KooHong Lee ,  JaeHak Yee ,  YoungChul Kim ,  Lan Hoang ,  Pandi C. Marimuthu ,  Steve Anderson ,  HunTeak Lee ,  HeeJo Chi

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L21/78 ,  H01L23/31

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012

摘要： A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.

公开(公告)号：US09524958B2

公开(公告)日：2016-12-20

申请号：US13928862

申请日：2013-06-27

申请人： STATS ChipPAC, Ltd.

发明人： JoonYoung Choi ,  YongHee Kang ,  HunTeak Lee ,  KeonTaek Kang ,  YoungChul Kim

IPC分类号： H01L21/76 ,  H01L29/24 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L25/50 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes a carrier with an interface layer applied over the carrier. The interface layer can include non-conductive paste or non-conductive film. A plurality of semiconductor die is mounted to the carrier and interface layer by pressing the semiconductor die to the carrier and interface layer for one second or less, and simultaneously thermal compression bonding multiple semiconductor die to the carrier and interface layer for 5-10 seconds. By pressing the semiconductor die to the interface layer for a short period of time and then simultaneously thermal compression bonding multiple semiconductor die to the interface layer for a second longer period of time, the overall throughput of die bonding increases to process more die per unit of time. An encapsulant is deposited over the semiconductor die. The carrier is removed and interconnect structure is formed over the semiconductor die and encapsulant.

摘要翻译： 半导体器件包括具有施加在载体上的界面层的载体。 界面层可以包括非导电浆料或非导电膜。 将多个半导体管芯通过将半导体管芯压入载体和界面层1秒以下，同时将多个半导体管芯与载体和界面层热粘合5-10秒，从而安装在载体和界面层上。 通过将半导体管芯压入界面层一段较短的时间，然后同时将多个半导体管芯同时热压粘合到界面层上较长的时间段，芯片接合的总体生产量增加，以处理更多的单位 时间。 密封剂沉积在半导体管芯上。 移除载体并且在半导体管芯和密封剂上形成互连结构。

公开(公告)号：US20160163675A1

公开(公告)日：2016-06-09

申请号：US15012346

申请日：2016-02-01

申请人： STATS ChipPAC, Ltd.

发明人： KyungMoon Kim ,  KooHong Lee ,  JaeHak Yee ,  YoungChul Kim ,  Lan Hoang ,  Pandi C. Marimuthu ,  Steve Anderson ,  HunTeak Lee ,  HeeJo Chi

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012

摘要： A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.

摘要翻译： 半导体器件具有设置在载体上的多个半导体管芯。 在半导体管芯上方形成诸如柱形凸块的电互连。 螺柱凸块被修剪成均匀的高度。 衬底包括在衬底上的凸块。 将半导体管芯的电气互连结合到衬底的凸块上，同时将半导体管芯设置在载体上。 在半导体管芯和衬底之间沉积底部填充材料。 或者，使用追逐模具在半导体管芯和衬底上沉积密封剂。 半导体管芯的凸起凸块与衬底的凸起的接合是使用回流焊或热压而进行的，同时半导体管芯是重新构成的晶片形式并且附着到载体上，以提供与衬底的倒装芯片型互连的高通量。

公开(公告)号：US20150001703A1

公开(公告)日：2015-01-01

申请号：US13928862

申请日：2013-06-27

申请人： STATS ChipPAC, Ltd.

发明人： JoonYoung Choi ,  YongHee Kang ,  HunTeak Lee ,  KeonTaek Kang ,  YoungChul Kim

IPC分类号： H01L25/00 ,  H01L25/065

CPC分类号： H01L25/50 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes a carrier with an interface layer applied over the carrier. The interface layer can include non-conductive paste or non-conductive film. A plurality of semiconductor die is mounted to the carrier and interface layer by pressing the semiconductor die to the carrier and interface layer for one second or less, and simultaneously thermal compression bonding multiple semiconductor die to the carrier and interface layer for 5-10 seconds. By pressing the semiconductor die to the interface layer for a short period of time and then simultaneously thermal compression bonding multiple semiconductor die to the interface layer for a second longer period of time, the overall throughput of die bonding increases to process more die per unit of time. An encapsulant is deposited over the semiconductor die. The carrier is removed and interconnect structure is formed over the semiconductor die and encapsulant.

摘要翻译： 半导体器件包括具有施加在载体上的界面层的载体。 界面层可以包括非导电浆料或非导电膜。 将多个半导体管芯通过将半导体管芯压入载体和界面层1秒以下，同时将多个半导体管芯与载体和界面层热粘合5-10秒，从而安装在载体和界面层上。 通过将半导体管芯压入界面层一段较短的时间，然后同时将多个半导体管芯同时热压粘合到界面层上较长的时间段，芯片接合的总体生产量增加，以处理更多的单位 时间。 密封剂沉积在半导体管芯上。 移除载体并且在半导体管芯和密封剂上形成互连结构。

公开(公告)号：US09287204B2

公开(公告)日：2016-03-15

申请号：US14039092

申请日：2013-09-27

申请人： STATS ChipPAC, Ltd.

发明人： KyungMoon Kim ,  KooHong Lee ,  JaeHak Yee ,  YoungChul Kim ,  Lan Hoang ,  Pandi C. Marimuthu ,  Steve Anderson ,  HunTeak Lee ,  HeeJo Chi

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012

摘要： A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.

摘要翻译： 半导体器件具有设置在载体上的多个半导体管芯。 在半导体管芯上方形成诸如柱形凸块的电互连。 螺柱凸块被修剪成均匀的高度。 衬底包括在衬底上的凸块。 将半导体管芯的电气互连结合到衬底的凸块上，同时将半导体管芯设置在载体上。 在半导体管芯和衬底之间沉积底部填充材料。 或者，使用追逐模具在半导体管芯和衬底上沉积密封剂。 半导体管芯的凸起凸块与衬底的凸起的接合是使用回流焊或热压而进行的，同时半导体管芯是重新构成的晶片形式并且附着到载体上，以提供与衬底的倒装芯片型互连的高通量。

公开(公告)号：US09236332B2

公开(公告)日：2016-01-12

申请号：US13765594

申请日：2013-02-12

申请人： STATS ChipPAC, Ltd.

发明人： Reza A. Pagaila ,  KiYoun Jang ,  HunTeak Lee

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/4952 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05155 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48249 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure.

公开(公告)号：US09252130B2

公开(公告)日：2016-02-02

申请号：US13853810

申请日：2013-03-29

申请人： STATS ChipPAC, Ltd.

发明人： KyungMoon Kim ,  YoungChul Kim ,  HunTeak Lee ,  KeonTaek Kang ,  HeeJo Chi

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75704 ,  H01L2224/75705 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/81805 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Methods of producing a semiconductor package using dual-sided thermal compression bonding includes providing a substrate having an upper surface and a lower surface. A first device having a first surface and a second surface can be provided along with a second device having a third surface and a fourth surface. The first surface of the first device can be coupled to the upper surface of the substrate while the third surface of the second device can be coupled to the lower surface of the substrate, the coupling occurring simultaneously to produce the semiconductor package.

摘要翻译： 使用双面热压接的半导体封装的制造方法包括提供具有上表面和下表面的基板。 具有第一表面和第二表面的第一装置可以与具有第三表面和第四表面的第二装置一起提供。 第一器件的第一表面可以耦合到衬底的上表面，而第二器件的第三表面可以耦合到衬底的下表面，耦合同时发生以产生半导体封装。

公开(公告)号：US20140295618A1

公开(公告)日：2014-10-02

申请号：US13853810

申请日：2013-03-29

申请人： STATS CHIPPAC, LTD.

发明人： KyungMoon Kim ,  YoungChul Kim ,  HunTeak Lee ,  KeonTaek Kang ,  HeeJo Chi

IPC分类号： H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75704 ,  H01L2224/75705 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/81805 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Methods of producing a semiconductor package using dual-sided thermal compression bonding includes providing a substrate having an upper surface and a lower surface. A first device having a first surface and a second surface can be provided along with a second device having a third surface and a fourth surface. The first surface of the first device can be coupled to the upper surface of the substrate while the third surface of the second device can be coupled to the lower surface of the substrate, the coupling occurring simultaneously to produce the semiconductor package.

摘要翻译： 使用双面热压接的半导体封装的制造方法包括提供具有上表面和下表面的基板。 具有第一表面和第二表面的第一装置可以与具有第三表面和第四表面的第二装置一起提供。 第一器件的第一表面可以耦合到衬底的上表面，而第二器件的第三表面可以耦合到衬底的下表面，耦合同时发生以产生半导体封装。

公开(公告)号：US20140175640A1

公开(公告)日：2014-06-26

申请号：US14039092

申请日：2013-09-27

申请人： STATS ChipPAC, Ltd.

发明人： KyungMoon Kim ,  KooHong Lee ,  JaeHak Yee ,  YoungChul Kim ,  Lan Hoang ,  Pandi C. Marimuthu ,  Steve Anderson ,  HunTeak Lee ,  HeeJo Chi

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012

摘要： A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.

摘要翻译： 半导体器件具有设置在载体上的多个半导体管芯。 在半导体管芯上方形成诸如柱形凸块的电互连。 螺柱凸块被修剪成均匀的高度。 衬底包括在衬底上的凸块。 将半导体管芯的电气互连结合到衬底的凸块上，同时将半导体管芯设置在载体上。 在半导体管芯和衬底之间沉积底部填充材料。 或者，使用追逐模具在半导体管芯和衬底上沉积密封剂。 半导体管芯的凸起凸块与衬底的凸起的接合是使用回流焊或热压而进行的，同时半导体管芯是重新构成的晶片形式并且附着到载体上，以提供与衬底的倒装芯片型互连的高通量。

公开(公告)号：US20130256840A1

公开(公告)日：2013-10-03

申请号：US13906489

申请日：2013-05-31

申请人： STATS ChipPAC, Ltd.

发明人： JaEun Yun ,  HunTeak Lee ,  SeungYong Chai ,  WonJun Ko

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3121 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02317 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1416 ,  H01L2224/16225 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/4805 ,  H01L2224/48091 ,  H01L2224/481 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/01014 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/11

摘要： A semiconductor device has a build-up interconnect structure formed over an active surface of a semiconductor wafer containing a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the interconnect structure. Bumps are formed over the interconnect structure. A protective coating material is deposited over the insulating layer and saw street. A lamination tape is applied over the coating material. A portion of a back surface of the semiconductor wafer is removed. A mounting tape is applied over the back surface. The lamination tape is removed while leaving the coating material over the insulating layer and saw street. A first channel is formed through the saw street extending partially through the semiconductor wafer. The coating material is removed after forming the first channel. A second channel is formed through the saw street and the mounting tape is removed to singulate the semiconductor wafer.

摘要翻译： 半导体器件具有形成在半导体晶片的有源表面上的积聚互连结构，该半导体晶片包含由锯街隔开的多个半导体管芯。 在互连结构上形成绝缘层。 在互连结构上形成凸起。 保护涂层材料沉积在绝缘层和锯条之上。 层压胶带涂在涂料上。 去除半导体晶片的背面的一部分。 安装带应用在背面上。 除去层压带，同时将涂层材料留在绝缘层和锯条上。 通过部分穿过半导体晶片延伸的锯条形成第一通道。 在形成第一通道之后去除涂层材料。 通过锯道形成第二通道，并且去除安装带以划分半导体晶片。